Samsung Electronics Co., Ltd.

Moon-han Park

Tai-su Park

Seung-Hwan Lee

Jae-Yoon Yoo

Han-sin Lee

Ho Young Lee

Weon-hong Kim

Hwa-Sung Rhee

Ha-Jin Lim

Yu-gyun Shin

Kyung-won Park

Jin-Ho Do

Ho Joong Lee

Hyun-Suk Kim

In-seak Hwang

Hwa-sung Rhee

Dong-ho Ahn

Sung-eui Kim

Moon-kyun Song

Dae-Kwon Joo

Dong-hoon Khang

Dong-woo Kang

Ueno Tetsuji

Keum-joo Lee

Young-sun Koh

Ji-ho Yoo

Nae-in Lee

Chang-ki Hong

Min-Woo Song

Hyung-suk Jung

Tetsuji Ueno

Pan-Kwi Park

Hyun-suk Kim

Young-wug Kim

Sug-hun Hong

Koung-min Ryu

Seon-Bae Kim

Chong-Kwang Chang

Ho-kyu Kang

Kwan-young Oh

Kyung-il Hong

Jung-yup Kim

Moon-Kyun Song

Jong-hoon Baek

Su-Young Choi

Jin-ho Do

Eun-Gon Kim

To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.

Method of manufacturing integrated circuit device

An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.

A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.

Semiconductor device having insulating pattern and method of forming the same

Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

Methods of manufacturing semiconductor devices

In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.

Methods of forming MOSFET devices using nitrogen-injected oxide layers to form gate insulating layers having different thicknesses

There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Method of patterning a semiconductor device with hard mask

A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.

Methods of forming gate structure and methods of manufacturing semiconductor device including the same

An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Method of forming an at least penta-sided-channel type of FinFET transistor

The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Transistors for semiconductor device and methods of fabricating the same

At least penta-sided-channel type of FinFET transistor

In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

MOS transistor with elevated source/drain structure

Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process

Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

Trench isolation regions having recess-inhibiting layers therein that protect against overetching

Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing

A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 &angst; is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

Trench isolation regions having trench liners with recessed ends

Growing community of inventors

Yongin-si, South Korea

Moon-han Park