Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Mosel Vitelic Corporation

Mong-Song Liang

Chen-Jong Wang

Kong-Beng Thei

Ching-Hsiang Hsu

Jin-Yuan Lee

Shou-Gwo Wuu

Harry Chuang

Chung-Hui Su

Shyh-Chyi Wong

Shih-Chang Chen

Liang-Gi Yao

Ming-Yuan Wu

Chiung-Han Yeh

Chue-San Yoo

Ruei-Ling Lin

Shau-Lin Shue

Syun-Ming Jang Jang

Steve S Chung

Tze-Liang Lee

Sheng-Chen Chung

Jing-Cheng Lin

Harry-Hak-Lay Chuang

Ching-Hua Hsieh

Cheng-Lin Huang

Tien-Chih Chang

Yee-Chia Yeo

Chenming Hu

Fu-Liang Yang

Yean-Kuen Fang

Chung Long Cheng

Winston Shue

Kuen-Chyr Lee

Chen-Hua Douglas Yu

Chih-Tang Peng

Kuo Ching Huang

Julie Huang

Dun-Nian Yaung

Hun-Jan Tao

Ryan Chia-Jen Chen

Chao-Hsiung Wang

Ming-Hua Yu

Di-Son Kuo

Chrong-Jung Lin

Jr-Hung Li

Chien-Chao Huang

Ming-Fang Wang

Chung-Shi Liu

Jhon-Jhy Liaw

Mei-Yun Wang

Chao-Cheng Chen

Chih-Wei Chang

Yung-Cheng Lu

Tai-Chun Huang

Ming-Hsing Tsai

Chun-Chieh Lin

Kuo-Tai Huang

Hsien-Ming Lee

Shing-Chyang Pan

Cheng-Ming Wu

Shui-Hung Chen

Chih-Hsiang Yao

Yi-Shien Mor

Chao-Hsien Peng

Hao-Ming Lien

Tse-Liang Ying

Mo-Chiun Yu

Li-Lin Su

Wen-Huei Guo

Jung-Hui Kao

Cheng-Yeh Shih

Tzung-Chi Lee

Shih-Wei Chou

Hung-Chih Tsai

Jane-Bai Lai

Chun-Yi Shih

Charles C-h Hsu

Mou-Shiung Lin

Chii-Horng Li

Huan-Just Lin

Da-Yuan Lee

Ling-Yen Yeh

Weng Chang

Chien-Hao Chen

Kuo-Ching Huang

Zhen-Cheng Wu

Chi-Chun Chen

Ting-Wah Wong

Yuan-Chang Huang

Minghsing Tsai

Chien-Liang Chen

Chia-Lin Chen

Matt Yeh

Chin-Chiu Hsia

Ming-Han Liao

ChaoChieh Tsai

Hou-Ju Li

Chung-Long Cheng

Wen-Chih Yang

Kuan-Shou Chi

Fu Chin Yang

A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Strained isolation regions

A device having a gate where the profile of the gate provides a first width at a top region and a second width at a bottom region is described. The gate may include tapered sidewalls. The gate may be a metal gate structure.

Integrated circuit metal gate structure having tapered profile

A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

SRAM devices utilizing strained-channel transistors and methods of manufacture

A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Dishing-free gap-filling with multiple CMPs

A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Layout methods of integrated circuits having unit MOS devices

A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Process to make high-K transistor dielectrics

A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

Integrated circuit metal gate structure and method of fabrication

An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Semiconductor device and method of fabricating same

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Integrating a first contact structure in a gate last process

A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Relaxed silicon germanium substrate with low defect density

Growing community of inventors

Hsin-Chu, Taiwan

Mong-Song Liang