Infineon Technologies Ag

Momtchil Stavrev

Mirko Vogt

Stephan Wege

Oliver Genz

Alexander Reb

Dirk Meinhold

Maik Stegemann

Hans-Peter Moll

Christian Bretthauer

Markus M Kirchhoff

Werner Graf

Kristin Schupke

Lars Heineck

Holger Poehle

Barbara Schmidt

Stefan Gruss

Hans-Georg Fröhlich

Percy Heger

Stephan Machill

Matthias Handke

Antje Laessig

Bernhard Laumer

A semiconductor die is proposed, wherein the semiconductor die comprises a microelectronic section and a sensor section. The microelectronic section comprises an integrated circuit. The sensor section adjoins an edge of the semiconductor die. A sensor is also proposed, which comprises such a semiconductor die.

Semiconductor die with sensor section located at the edge

A semiconductor die includes a last metallization layer above a semiconductor substrate, a bond pad above the last metallization layer, a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad, an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad, and an electrically conductive interconnection structure that extends from the bond pad to the upper metallization layer outside the contact area of the bond pad. Corresponding methods of manufacture are also provided.

Semiconductor die bond pad with insulating separator

A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Method for production of a semiconductor structure

Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask

Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Method for fabricating a contact hole plane in a memory module

Growing community of inventors

Dresden, Germany

Momtchil Stavrev