Cadence Design Systems, Inc.

Mohit Mittal

Anujan Varma

Steven Lee Shrader

An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2), and operations i) through iii) are repeated using the next r different field elements of the partition.

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Punjab, India

Mohit Mittal