Lsi Logic Corporation

Cisco Technology, Inc.

Lsi Corporation

Mohan R Nagar

Mudasir Ahmad

Aritharan Thurairajaratnam

Kuo-Chuan Liu

Bangalore J Shanker

Jie Xue

Sarathy Rajagopalan

Mukul A Joshi

Farshad Ghahghahi

Anand Govind

Weidong Xie

Shirish Shah

An apparatus for grounding a chip may be provided. The apparatus may comprise a ground lid, a ground trace, a first substance, and a second substance. The first substance may be configured adhere the ground lid to the ground trace. The second substance may be configured to provide electrical conduction between the ground lid and the ground trace.

Ground lid opening on a substrate

A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.

Method and apparatus for supporting a computer chip on a printed circuit board assembly

An integrated circuit package apparatus includes a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.

Integrated circuit package lid configured for package coplanarity

To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.

Lid for an electrical hardware component

A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring substantially surrounding a circumference of the semiconductor wafer and having a width that varies in order to avoid overlap near edge die areas of the semiconductor wafer.

System and method for increasing yield from semiconductor wafer electroplating

A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Integrated circuit package design

A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.

Measurement of package interconnect impedance using tester and supporting tester

A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor. The electrically conductive cantilever ground pins also have tips, for making electrical connections with electrically conductive structures on the package substrate that surround the electrically conductive structure to be tested on the package substrate.

Substrate impedance measurement

Integrated circuit package design with non-orthogonal die cut out

A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer. A first of pins is connected to the signal contact, for making a connection with a structure to be tested on the package substrate. Others of the pins are connected to the ground contacts, for making connections with structures on the package substrate that surround the structure to be tested.

An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.

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Cupertino, CA, United States of America

Mohan R Nagar