Taiwan Semiconductor Manufacturing Comp. Ltd.

Motorola Corporation

Mohammed Rabiul Islam

Stefan Rusu

Weiwei Song

Suresh Venkatesan

Janos Farkas

Venkat Kolagunta

Rajesh Tiwari

Brian George Anthony

John Mendonca

Abbas Guvenilir

Kumar Lalgudi

Ranjith Kumar

Jianyang Xu

Wei-wei Song

Chih-Tsung Shih

Eric Soenen

Bradley Paul Smith

Matthew Thomas Herrick

Cindy Reidsema Simpson

Rina Chowdhury

Bradley P Smith

Marijean E Azrak

Robert Douglas Mikkola

Edward Acosta

David Moralez Pena

Brett Caroline Baker

Cindy Kay Goldberg

Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.

Structures and methods for high speed interconnection in photonic systems

A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Logic cell structures and related methods

Disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die (pDie) and an electronic die (eDie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. In one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. In another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. In these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.

Apparatus and methods for optical interconnects

A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

Photonic semiconductor device and method

A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

Three-dimensional integrated circuit (3D IC) low-dropout (LDO) regulator power delivery

Heterogeneous packaging integration of photonic and electronic elements is described herein. In one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. The second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.

Heterogeneous packaging integration of photonic and electronic elements

A copper interconnect polishing process begins by polishing ( ) a bulk thickness of copper ( ) using a first platen. A second platen is then used to remove ( ) a thin remaining interfacial copper layer to expose a barrier film ( ). Computer control ( ) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed ( ) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier ( ) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations ( ). A scrubbing operation ( ) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces ( and ) between these layers ( and ) and their adjacent dielectric layers ( and ) are positioned in the stack ( ) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack ( ). Etch processing is then used to position the layers ( ) and ( ) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Method for forming a dual inlaid copper interconnect structure

A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (,, and,) between these layers (,and,) and their adjacent dielectric layers (,and,) are positioned in the stack (,) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (,). Etch processing is then used to position the layers (,) and (,) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Growing community of inventors

Austin, TX, United States of America

Mohammed Rabiul Islam