Nippon Soken, Inc.

Nippon Steel Corporation

Mitutaka Katada

Tadashi Hattori

Kazuhiro Tsuruta

Masami Yamaoka

Seizi Huzino

Seiji Fujino

Nobuyoshi Sakakibara

Minoru Ohta

Takayuki Tominaga

A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

Semiconductor substrate structure for producing two isolated circuits on

A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Semiconductor power device having walls of an inverted mesa shape to

A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by an burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

Semiconductor circuit structure and method for making the same

Semiconductor device and a method for producing the same

In a method of producing a semiconductor device, an amorphous silicon layer is deposited on a polycrystalline silicon layer formed on an insulator layer (SiO.sub.2). Ions are implanted into the amorphous silicon layer while heat treating the amorphous silicon layer at a low temperature thereby forming a solid-phase growth layer, and a transistor is formed of the solid-phase growth layer.

Polycrystalline silicon active layer for good carrier mobility

In a semiconductor device having mainly vertical semiconductor elements, a plurality of semiconductor elements are formed in spaced relationship from each other on an insulation layer formed on a substrate and therefore completed isolated electrically from each other. A plurality of semiconductor intermetallic compound layers used as electrodes are formed independently in the same spaced relationship as the semiconductor elements for the respective semiconductor elements, making it possible to determine the potential for each semiconductor element as desired. Both N-type DMOS and P-type DMOS or the like can thus be formed on a single seminconductor single crystal substrate.

Growing community of inventors

Nishio, Japan

Mitutaka Katada