Intel Corporation

Mitul Bharat Modi

Omkar G Karhade

Edvin Cetegen

Debendra Mallik

Nitin A Deshpande

Robert L Sankman

Rajendra C Dias

Sankara J Subramanian

Ravindranath Vithal Mahajan

Sanka Ganesan

Eric Jin Li

Ram S Viswanath

Digvijay Ashokkumar Raorane

Joshua Heppner

Amruthavalli Pallavi Alur

Nicholas S Haehn

Robert M Nickerson

Nicholas Neal

Carolyn R McCormick

Sri Chaitra J Chavali

Patricia A Brusso

Ruben Cadena

Shawna M Liff

Wei Ey Li

Rajasekaran Swaminathan

Yiqun Bai

Aastha Uppal

Srinivas V Pietambaram

Kemal Aygun

Sairam Agraharam

Yikang Deng

Chung-Hao Chen

Biju Chandran

Li-Sheng Weng

Manish Dubey

Xiaoqian Li

Bharat P Penmecha

Richard J Harries

Shankar Ganapathysubramanian

Edward L Martin

Emile Davies-Venn

Sudarshan V Rangaraj

Kumar Abhishek Singh

Jan Krajniak

Zhichao Zhang

William J Lambert

Brandon C Marin

James Chris Matayabas, Jr

Je-Young Chang

Jeremy D Ecton

Tarek A Ibrahim

Christopher L Rumer

Dingying David Xu

Zhimin Wan

Anna M Prakash

Weihua Tang

Bai Nie

Takashi Kumamoto

Zhenguo Jiang

Thomas J De Bonis

Ziyin Lin

Malavarayan Sankarasubramanian

Haifa Hariri

Sri Chaitra Chavali

Shenavia S Howell

Susmriti Das Mahapatra

John Harper

Wei Li

Joseph Van Nausdle

Vaibhav Agrawal

Yoshishiro Tomita

Nazmiye Acikgoz Akbay

Fadi Y Hafez

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Photonic integrated circuit packaging architectures

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

Mold shelf package design and process flow for advanced package architectures

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

Open cavity bridge co-planar placement architectures and processes

No mold shelf package design and process flow for advanced package architectures

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

Dummy die structures of a packaged integrated circuit device

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads, and an open cavity. A bridge die is in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, a power delivery bridge pad between the first plurality of bridge pads and the second plurality of bridge pads, and conductive traces. A first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads. A second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads. A power delivery conductive line is coupled to the power delivery bridge pad.

Open cavity bridge power delivery architectures and processes

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

Substrate with thermal insulation

Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

Active package cooling structures using molded substrate packaging technology

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Stacked die cavity package

A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.

Wideband multi-pin edge connector for radio frequency front end module

Growing community of inventors

Phoenix, AZ, United States of America

Mitul Bharat Modi