Sumitomo Electric Industries, Limited

Sumitomo Electric Printed Circuits, Inc.

National Institute of Advanced Industrial Science and Technology

Mitsutaka Tsubokura

Koji Nitta

Shoichiro Sakai

Junichi Motomura

Akira Tsuchiko

Mari Sogabe

Masashi Iwamoto

Masatoshi Majima

Makoto Kiyama

Tomoyuki Awazu

Takayuki Nishiura

Takayasu Sugihara

Masahiro Yamakawa

Osamu Mizuno

Shinya Fujiwara

Kohji Inokuchi

Tetsuo Oishi

Masashi Yamashita

Kenichi Miyahara

A printed wiring board includes a base layer having insulating properties, a first conductive layer directly or indirectly stacked on the base layer front surface, and including a copper foil, a second conductive layer directly or indirectly stacked on the base layer back surface, and including a copper foil, a stacked body for a via hole, the stacked body being stacked on an inner periphery and a bottom of a connection hole that extends through the first conductive layer and the base layer in a thickness direction, and being configured to electrically connect the first conductive layer and the second conductive layer to each other, and having an electroless copper plating layer. Each copper foil contains a copper crystal grain oriented in a plane orientation, and an average crystal grain size of copper of each copper foil is 10 μm or greater, the electroless copper plating layer includes palladium.

Printed wiring board

The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 μm or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 μg/cmor more and 0.40 μg/cmor less.

Printed circuit board

A method for separating metal components from a treatment material containing a silicate and metal elements includes: a reaction step of reacting the treatment material and a molten alkali hydroxide in which bubbles due to water vapor derived from water are generated by heating a hydroxide of an alkali metal or an alkaline-earth metal and the water in a state where the hydroxide and the water coexist, to obtain a reaction product; and a first precipitation step of dissolving the reaction product of the treatment material and the molten alkali hydroxide after the reaction step in water, thereby generating a precipitate containing the metal elements.

Method for separating metal components

A magnesium alloy sheet is made of a magnesium alloy containing Al. Particles of an intermetallic compound containing at least one of Al and Mg are present in the sheet in a dispersed state. The sheet includes an oxide film which extends substantially over the surface of the sheet and which has a uniform thickness. The average size of the particles of the intermetallic compound is 0.5 &#x3bc;m or less. The percentage of the total area of the particles is 11% or less. Therefore, the magnesium alloy sheet is excellent corrosion resistance. A magnesium alloy structural member is provided.

Magnesium alloy sheet

An object is to provide a compound semiconductor substrate and a surface-treatment method thereof, in which, even after the treated substrate is stored for a long period of time, resistance-value defects do not occur. Even when the compound semiconductor substrate is stored for a long period of time and an epitaxial film is then formed thereon, electrical-characteristic defects do not occur. The semiconductor substrate according to the present invention is a compound semiconductor substrate at least one major surface of which is mirror-polished, the mirror-polished surface being covered with an organic substance containing hydrogen (H), carbon (C), and oxygen (O) and alternatively a compound semiconductor substrate at least one major surface of which is mirror-finished, wherein a silicon (Si) peak concentration at an interface between an epitaxial film grown at a growth temperature of 550&#xb0; C. and the compound semiconductor substrate is 2&#xd7;10cmor less.

Compound semiconductor substrate

Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve representing the relation between a voltage applied to the obverse face of a wafer serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve is found through applying a voltage to the reverse face of the wafer . The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount for the wafer , found from the first C-V curve and the second C-V curve

Method and device for determining backgate characteristics

Growing community of inventors

Itami, Japan

Mitsutaka Tsubokura