Denso Corporation

Nippondenso Co., Ltd.

Nippon Soken, Inc.

Shin-etsu Handotai Co., Ltd.

Mitsutaka Katada

Hidetoshi Muramoto

Tsutomu Kawaguchi

Tadashi Hattori

Seiji Fujino

Katsunori Abe

Takeshi Kuzuhara

Yasushi Higuchi

Kazuhiro Tsuruta

Hiroyuki Yamane

Noriyuki Iwamori

Seizi Fuzino

Takayoshi Naruse

Tetsuo Fujii

Yukihiko Watanabe

Nobuhiko Noto

Hiroshi Takeno

Kazuhiko Yoshida

Masaki Matsui

Akiyoshi Asai

Michitoshi Onoda

Nobuyuki Ohya

Shigemitsu Fukatsu

Hiroyasu Itou

Akira Tai

Atsushi Komura

Yukiaki Yogo

Hiroshi Ohtsuki

In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

SOI (silicon on insulator) structure semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.

Semiconductor device including a plurality of memory cells with no difference in erasing properties

A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.

Nonvolatile semiconductor memory device and method of erasing and programming the same

A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Semiconductor device, wiring of semiconductor device, and method of forming wiring

A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

EEPROM and EEPROM manufacturing method

In a nonvolatile semiconductor memory, a floating gate electrode is disposed above a silicon substrate between source and drain regions, through a tunnel film, and a control gate electrode is disposed above the floating gate electrode through an insulating film. The substrate is grounded and at least two negative voltages are respectively applied to the control gate electrode, so that a voltage is applied to the tunnel film. In these cases, charge retention properties are evaluated. The voltages applied to the control gate electrode are controlled so that the voltage applied to the tunnel film does not exceed a voltage applied to the tunnel film during a memory operation. A charge retention property when no voltage is applied across the control gate electrode and the substrate, i.e., when no voltage is externally applied to the tunnel film, is estimated by the charge retention properties when the two voltages are applied to the control gate electrode.

Charge retention lifetime evaluation method for nonvolatile semiconductor memory

A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Semiconductor device and fabrication process thereof

A semiconductor memory device comprising a source and a drain formed in a P-type semiconductor substrate and a floating gate and a control gate constituting a two-layer gate. Electric-field moderating layer is provided in the P-type semiconductor substrate to contact with a side face of the drain. P-type region is formed in contact with channel region side surface and bottom surface of the electric-field moderating layer. P-type region lower part of the P-type region in contact with the bottom surface of the electric-field moderating layer is given a lower impurity concentration than P-type region side part formed at the channel region side of the electric-field moderating layer. By this means it is possible to increase the writing speed of the semiconductor memory device while suppressing delay in the switching speed during reading operation.

Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Method of fabricating a MIS transistor

A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

Semiconductor device with conductive connecting layer and abutting

Enhancement-type semiconductor having reduced leakage current

Process for fabricating a complementary MIS transistor

In a method of bonding semiconductor substrates, a plurality of the semiconductor substrates are first prepared. Surfaces of the semiconductor substrates are mirror-polished. The mirror-polished surface of at least one of the semiconductor substrates is then provided with a hydrophilic property in such a way that an oxide layer is formed on the mirror-polished surface by exposing the mirror-polished surface to an atmosphere of at least one of an oxygen ion and an oxygen radical. A water molecule is then adhered to the mirror-polished surface. The semiconductor substrates then contact with each other through the mirror-polished surface. The contacted semiconductor substrates are then heated. According to such a method of bonding, the semiconductor substrates are strongly bonded to each other with hardly an unbonded region even if the semiconductor substrates are heated at a low temperature.

Method of bonding semiconductor substrates

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Complementary MIS transistor and a fabrication process thereof

A dielectric buried layer is formed inside substrates which are directly bonded together. Firstly, a groove or a recess, or both are formed on the principal bonding plane of one of at least two kinds of semiconductor substrates to be bonded together. Once the semiconductor substrates are bonded together, the groove and recess form a space, which is filled with dielectric. Before forming the dielectric buried layer, the invention carries out a process of removing potential damage from corners of the groove and/or recess.

Growing community of inventors

Hoi-gun, Japan

Mitsutaka Katada