Nec Corporation

Tokyo Ohka Kogyo Co., Ltd.

Mitsuru Kimura

Kazuhiro Ikuina

Hiroshi Komano

Kazuaki Utsumi

Koji Matsui

Akinobu Shibuya

Ichiro Hazeyama

Toshimi Aoyama

Eiichi Ogawa

Tatsuo Inoue

Shoji Nakakita

A ceramic substrate for use with a semiconductor device, includes an electrical conductor composed of Ag, a resistor composed of oxide, and a barrier layer located between the electrical conductor and the resistor and composed of a material selected from a group consisting of AgPd and AgPt. The ceramic substrate prevents a diffusion of Ag atoms between the electrical conductor and the resistor, and hence provides a stable internal resistance.

Ceramic substrate for semiconductor device

A multi-layer wiring substrate includes an insulating layer which is essentially formed of a silica sintered product, and a conductor layer formed on an upper surface of the insulating layer from an electrically conductive material. The multi-layer wiring substrate is produced by forming a green sheet from a starting powder such as an ultrafine powder of amorphous silica having an average particle size of several to tens nm, and firing or calcining the green sheet at a temperature of 800.degree. to 1,200.degree. C. in an atmosphere containing steam to provide a silica sintered product which is sintered to a sufficient extent and has a high strength. The starting powder has a composition which comprises 95.0 to 99.5% by weight of a fine silica powder, 0.05 to 5.0% by weight of an alkaline earth metal compound, or comprises 95.0 to 99.0% by weight of a fine silica powder and 1.0 to 5.0% by weight of B.sub.2 O.sub.3. The silica sintered product has a sufficiently high strength and a dielectric constant of 4.0 at 1 MHz.

Multi-layer wiring substrate, and process for producing the same

A process for producing a silica sintered product for a multi-layer wiring substrate of the invention includes: providing a fine silica powder having an average particle size of 5 to 500 nm and a fine crystallized quartz powder having an average particle size 1 to 10 .mu.m, the fine crystallized quartz powder having a volume equal to 1 to 20% of the entire volume of the fine silica powder and the fine crystallized quartz powder; mixing the fine silica powder and the fine crystallized quartz powder with a binder and a solvent to form a silica-containing slurry; forming a green sheet by slip-casting the silica-containing slurry; and firing the green sheet at a temperature of 800.degree. to 1200.degree. C. in an atmosphere containing steam at a partial pressure of 0.005 to 0.85 atm.

Process for producing a silica sintered product for a multi-layer wiring

A via-structure off a multilayer interconnection ceramic substrate for a multi-chip module, a semiconductor package and an insulating substrate has a high strength and a high reliability being produced at a low cost. A gap is provided at an interface between a via-conductor and ceramics, and filled with a resin. The resin is preferably of a thermosetting polyimide resin or a benzo-cyclo-butene resin.

Via-structure of a multilayer interconnection ceramic substrate

An integrated circuit connecting method that includes connecting electrode pads on an integrated circuit device to electrode terminals on a base with metal bumps interposed, the electrode terminals being formed in registry with the electrode pads. The method includes the steps of forming metal bumps on a surface of at least one of the electrode pads and the electrode terminals; covering the surface on at least one of the integrated circuit device side and the base side with a resin that cures upon exposure to active energy rays; patterning the resin to strip selectively the coating of the resin over one of the electrode pads and the electrode terminals; bringing the electrode pads and the electrode terminals into a face-to-face relationship, allowing the metal bumps to contact one of the opposing electrode pads and electrode terminals, performing thermocompressing so that the resin coating will adhere closely to one of the integrated circuit device and the base while, at the same time, the electrode pads are connected to the electrode terminals with the metal bumps interposed; and performing at least one of heat treatment and exposure to active energy rays.

Method of bonding circuit boards

A multilayer glass ceramic substrate includes a glass ceramic layer and a plurality of conductive layers laminated via the glass ceramic layer. The glass ceramic layer is composed of inorganic compound consisting of aluminum oxide, borosilicate glass, anorthite crystal and celsian crystal wherein the aluminum oxide is contained in the range of 12 to 59.6 weight percent, the borosilicate glass is contained in the range of 18 to 69.6 weight percent, the anorthite crystal is contained in the range of 1 to 40 weight percent and the celsian crystal is contained in the range of 1 to 5 weight percent so that the total is 100 weight percent.

Mutlilayer glass ceramic substrate and method of fabricating the same

An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.

Element joining pad for semiconductor device mounting board

A method of bonding first and second circuit boards includes applying a light-sensitive adhesive over the first electrodes on a first circuit board and the areas where the first electrodes are not formed, and drying the applied adhesive to form a light-sensitive adhesive layer having the light-sensitive adhesive layer exposed selectively to active rays of light and performing development to remove only the light-sensitive adhesive layer on the first electrodes, and then performing a heat treatment to impart bonding quality to the light-sensitive adhesive layer remaining between adjacent first electrodes, placing the first and second circuit boards one on top of the other and thermocompressing the two circuit boards to have the first electrodes connected electrically to the second electrodes to form a single circuit board; and performing a heat treatment and/or exposure to active rays of light on the formed single circuit board.

A method for manufacturing a multichip package including the steps of forming a first polyimide insulating layer on a surface of a ceramic multilayer substrate having a circuit wiring therein, forming a first wiring connected to the circuit wiring of the multilayer substrate with a part of the first wiring being exposed at an open surface of the first polyimide insulating layer, forming a second polyimide insulating layer on a surface of a semiconductor element, and forming a second wiring connected with a circuit wiring of the semiconductor element in the second polyimide insulating layer with a part of the second wiring being exposed at an open surface of the second polyimide insulating layer. The method also includes positioning the semiconductor element on the substrate such that the part of the first wiring and the part of the second wiring oppose each other, and applying a predetermined pressure and a predetermined temperature in a predetermined gas atmosphere for a predetermined time period to cause the first and second polyimide layers to be cured and bonded with each other and to cause the parts of first and second wirings to be adhered to each other by thermal bonding.

Method of manufacturing a multichip package with increased adhesive

A fine-wired conductor for use in LSI circuits exhibits good adhesion properties. The conductor is made up of a film of metal such as chrome or titanium on an insulator such as a ceramic substrate, a gold layer over the film of metal and a palladium film on the gold layer. In addition, a palladium layer can be interposed between the metal film and the gold layer to facilitate gold plating and inhibit diffusion of the metal and the gold.

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Tokyo, Japan

Mitsuru Kimura