Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Mitsuru Kaneda

Tetsuo Takahashi

Kenji Suzuki

Hideki Takahashi

Koichi Nishi

Ryu Kamibaba

Katsumi Nakamura

Tadaharu Minato

Shinya Soneda

Yoshifumi Tomomatsu

Norifumi Tokuda

Mariko Umeyama

A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a ptype diffusion layer and an ntype source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the ntype source layer and the ptype diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the ptype diffusion layer is interposed between the p type channel doped layer and an ntype source layer, and the p type channel doped layer and the ntype source layer are not adjacent to each other.

Semiconductor device

A switching element control device for controlling a switching element incorporating a reverse conducting diode is provided. The switching element control device includes: a voltage detection circuit detecting a voltage across first and second main electrodes of the switching element; a comparator circuit comparing the voltage detected by the voltage detection circuit with a threshold voltage; and a drive circuit controlling driving of the switching element. The comparator circuit controls the drive circuit so that an on signal is not provided to the switching element when the detected voltage exceeds the threshold voltage.

Switching element control device

A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.

Semiconductor apparatus and method of manufacturing the same

A semiconductor device includes a drift layer formed of a first conductive type semiconductor material, a MOSFET part including a p-type base layer provided on a front surface of the drift layer, a first n-type buffer layer provided on a reverse side of the drift layer, and a second n-type buffer layer provided on a reverse side of the first n-type buffer layer and having a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of 1.0&#xd7;10cmor less.

Semiconductor device having improved safe operating areas and manufacturing method therefor

An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.

Semiconductor device and method of manufacturing the same

A semiconductor switching element includes a first gate electrode and a second gate electrode. The first gate electrode is disposed, via a first gate insulating film, inside a first trench that extends from an upper surface of an emitter region to reach a semiconductor layer, and intersects with the emitter region, a base region, and a charge storage layer. The second gate electrode is disposed, via a second gate insulating film, inside a second trench that extends from the upper surface of the emitter region and an upper surface of a conductive region to reach the semiconductor layer, and is adjacent to the emitter region, the base region, the charge storage layer, and the conductive region. The second trench is smaller in depth than the first trench, and the second trench is smaller in width than the first trench.

Semiconductor switching element and method of manufacturing the same

A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.

Semiconductor device preventing recovery breakdown and manufacturing method thereof

The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer. An emitter electrode is formed on the emitter region. The collector layer has thickness in the range between 17 &#x3bc;m to 50 &#x3bc;m.

Semiconductor device and manufacturing process thereof

A semiconductor device includes an n-type semiconductor substrate () including a p-type collector layer () formed in a second main surface side thereof, a trench () is formed in a peripheral portion of the semiconductor substrate () so as to surround the inside and reach the collector layer () from a first main surface of the semiconductor substrate (), and a p-type isolation region () formed by diffusion from a sidewall of the trench () is provided to be connected to the collector layer (). The trench () is filled with a filling material ().

Vertical semiconductor device and manufacturing method thereof

An N-type silicon substrate () has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N-type silicon substrate (), a P-type impurity diffusion layer () of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N-type silicon substrate (), a P-type isolation region () is partially formed by diffusing a P-type impurity. The P-type isolation region () has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (). As viewed from the upper surface side of the N-type silicon substrate (), the P-type isolation region () is formed, surrounding an Nregion () which is part of the N-type silicon substrate (). The Nregion () surrounded by the P-type isolation region () is defined as an element formation region of the N-type silicon substrate (). Thus obtained are a semiconductor device and a method of manufacturing the same, and a semiconductor substrate and a method of manufacturing the same, which make it possible to retain bidirectional breakdown voltages and ensure high reliability.

SEMICONDUCTOR SUBSTRATE WITH DEFECTS REDUCED OR REMOVED AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE CAPABLE OF BIDIRECTIONALLY RETAINING BREAKDOWN VOLTAGE AND METHOD OF MANUFACTURING THE SAME

Growing community of inventors

Tokyo, Japan

Mitsuru Kaneda