Adv Antest Corporation

Mitsuo Hori

Hideki Tada

Takahiro Kataoka

Hiroyuki Sekiguchi

Kazuo Mukawa

A test apparatus for testing an electronic device by providing test signals to the electronic device and comparing multiple output signals with respective anticipated values is disclosed, the test apparatus including: a reference timing detecting unit for detecting that one of the output signals has changed; a setting unit for setting beforehand a minimum time from changing of the output signal to changing of another output signal; an acquisition unit for acquiring the value of the latter output signal at a timing at which the minimum time has elapsed from detection of change of the former output signal; and a determination unit for determining the electronic device to be defective in the event that the value of the latter output signal thus acquired does not match the value which the latter output signal should assume following elapsing of the minimum time.

Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method

A test emulator for emulating a test of a semiconductor device is provided. The test emulator includes a test pattern providing means for providing a test pattern to a device simulator which simulates the operation of a semiconductor device, an expected value storage means for associating a comparison timing at which an output signal outputted from the device simulator according to the test pattern is compared with an predetermined expected value with the expected value at the comparison timing and previously storing therein the same, a margin determination means for determining the size of a margin between which the output signal corresponds to the expected value when the output signal corresponds to the expected value at the comparison timing and a notification means for notifying a user that the margin at the comparison timing is small when the size of margin is smaller than a reference value.

Test emulator, emulation program and method for manufacturing semiconductor device

A test simulator for simulating a test of a semiconductor device is disclosed, the test simulator including: a test pattern holding unit for holding an existing test pattern to be supplied to the semiconductor device; a device output holding unit for preliminarily holding an output to be obtained from the semiconductor device when the existing test pattern is supplied; a test pattern generating unit for generating a new test pattern to be supplied to the semiconductor device; a test pattern deciding unit for deciding whether the new test pattern is equal to the existing test pattern; and a simulation skipping unit for skipping at least a part of a simulation test by reading an output from the device output holding unit and using the output as an output for the new test pattern without supplying the new test pattern to the semiconductor device when the test patterns are equal to each other.

Test simulator, test simulation program and recording medium

A test program debugging apparatus of the present invention includes a device under test simulator and a semiconductor testing apparatus simulator. Further, the semiconductor testing apparatus simulator includes: a verification range acquiring unit that acquires a verification range that is a range of commands to be verified among commands included in the test program; a command simplifying unit that simplifies non-setting commands other than setting commands for setting the device under test simulator, among non-verification range commands included in a non-verification range that is a range other than the verification range within the test program; and a command executing unit that executes the verification range commands included in the verification range, the setting commands, and the non-setting commands simplified by the command simplifying unit.

Growing community of inventors

Tokyo, Japan

Mitsuo Hori