Elpida Memory, Inc.

Intermolecular, Inc.

Nec Corporation

Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Mitsuhiro Horikawa

Sandra Guy Malhotra

Hanhong Chen

Hiroyuki Ode

Xiangxin Rui

Kenichi Koyanagi

Wim Deweerd

Imran Hashim

David Chi

Isamu Asano

Yoshitaka Nakamura

Masahito Watanabe

Hiroshi Sakuma

Hidekazu Goto

Tsuyoshi Kawagoe

Keiji Kuroki

Karthik Ramani

Masashi Haruki

Shigeki Takishima

Shinichi Kihara

A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

DRAM MIM capacitor using non-noble electrodes

A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Methods to improve leakage for ZrO2 based high K MIM capacitor

A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.

Method of manufacturing semiconductor device

A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

High performance dielectric stack for DRAM capacitor

Disclosed is a method of manufacturing a semiconductor device formed by laminating a capacitor including a bottom metal electrode, a capacitive insulating film, and an upper metal electrode. When the capacitive insulating film is formed by performing a first step of forming a first dielectric layer on the bottom metal electrode by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric; and a second step of forming a second dielectric layer on the first dielectric layer by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric, a film forming temperature in the first step is set so as to be lower than a film forming temperature in the second step.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface.

A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film

There is prepared a wafer ( ) having a gettering capability such as PBS wafer having deposition of polysilicon on its back surface thereof, IG wafer containing oxygen precipitates. An element separation silicon oxide film ( ) is formed on the wafer ( ), and a first silicon oxide film ( ) is formed on the wafer ( ). Then the wafer ( ) is gradually cooled to a low temperature, or the wafer ( ) is cooled to a low temperature and then kept at the low temperature for a fixed time. Thereafter, the first silicon oxide film ( ) is removeed from the wafer ( ) and then the wafer ( ) is cleaned. Thereafter, a gate silicon oxide film ( ) and a gate electrode ( ) are formed. Subsequently, ion implantation to form a source ( ) and a drain ( ) and a heat treatment to activate implanted impurities are performed to form a basic MOS transistor.

Semiconductor device manufacturing method

In a method of manufacturing a semiconductor device, a first polysilicon film is formed on a surface of a semiconductor substrate for a semiconductor element to be formed thereon. Ion implantation is performed in such a manner that impurity ions are implanted into the semiconductor substrate surface through the first polysilicon film. The semiconductor substrate is heated to a first temperature after the step of performing ion implantation. Then, the semiconductor substrate is gradually cooled with a predetermined cooling rate at least from a second temperature to a third temperature while the semiconductor substrate is cooled from the first temperature. The second and third temperatures are lower than the first temperature. Subsequently, the polysilicon film is removed after the gradually cooling step.

Semiconductor manufacturing method including gettering of metal impurities

A semiconductor substrate is provided which maintains its gettering capabilities throughout the manufacturing process of a semiconductor device and which prevents previously gettered contaminating impurities from being released again into an operating region of a semiconductor device. The semiconductor substrate includes a silicon substrate, a polysilicon layer, and a high density boron layer. The silicon substrate has a first main surface and a second main surface opposed to the first main surface, and the silicon substrate is used to form a semiconductor device at least indirectly on the first main surface. The polysilicon film is formed at least indirectly on the second main surface, and the high density boron layer is disposed between the silicon substrate and the polysilicon film. Also a ratio of a highest boron density value in the high density boron layer to a lowest boron density value in the silicon substrate is greater than or equal to approximately 100. Instead of using the high density boron layer, other layers may be used such as silicon oxide layers or polysilicon layers. Also, a method for manufacturing the semiconductor substrate is also provided.

Semiconductor substrate and manufacturing method thereof

On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.

Growing community of inventors

Higashihiroshima, Japan

Mitsuhiro Horikawa