Taiwan Semiconductor Manufacturing Comp. Ltd.

Mirng-Ji Lii

Chen-Hua Douglas Yu

Ming-Da Cheng

Hao-Yi Tsai

Chung-Shi Liu

Chen-Shien Chen

Hsien-Wei Chen

Chien-Hsun Lee

Sheng-Yu Wu

Wei-Hung Lin

Tsung-Yuan Yu

Jiun Yi Wu

Wen-Hsiung Lu

Tsung-Ding Wang

Chien-Hsiun Lee

Tin-Hao Kuo

Yu-Feng Chen

Hsin-Hui Lee

Kuo-Ching Hsu

Ching-Hui Chen

Hung-Yi Kuo

Ching-Wen Hsiao

Kuo-Chin Chang

Chih-Wei Lin

Hung-Jui Kuo

Chao-Wen Shih

Chien Ling Hwang

Yen-Liang Lin

Kai-Chiang Wu

Ying-Ju Chen

Meng-Tse Chen

Jung Wei Cheng

Yu-min Liang

Kuo-Chung Yee

Ming-Che Ho

Chang-Jung Hsueh

Shih-Wei Liang

Tung-Liang Shao

Chin-Yu Ku

Szu Wei Lu

Yeong-Jyh Lin

Yi-Li Hsiao

Yu-Jen Tseng

Szu-Wei Lu

Po-Hao Tsai

Yi-Wen Wu

Yao-Chun Chuang

Ching-Jung Yang

Hui-Min Huang

Hon-Lin Huang

Chita Chuang

Hong-Seng Shue

Min-Chien Hsiao

Shin-Puu Jeng

Alexander Kalnitsky

Hsiu-Jen Lin

Tzuan-Horng Liu

Chun-Hung Lin

Mill-Jer Wang

Chih-Fan Huang

Yu-Peng Tsai

Hsin-Hung Liao

Chang-Pin Huang

Wei Sen Chang

Yung-Ping Chiang

Nien-Fang Wu

Yen-Chang Hu

Jui-Pin Hung

Han-Ping Pu

Chih-Hang Tung

Chun-Cheng Lin

Kuei-Wei Huang

Kuo-Chio Liu

Cheng-Ting Chen

Bor-Ping Jang

Hua-Shu Ivan Wu

Chung-Yi Lin

Hung-Jen Lin

Yi-Yang Lei

Han-Liang Tseng

Tsai-Tsung Tsai

Shang-Yun Hou

Pei-Haw Tsao

Yu-Chih Huang

Yu-Chia Lai

Yen-Ping Wang

Ming-Kai Liu

Kuo Lung Pan

Hsien-Ming Tu

Hao-Cheng Hou

Kuo-Lung Pan

Li-Huan Chu

Guan-Yu Chen

Clinton Chao

Chung Yu Wang

Chao-Hsiang Yang

Chen-Fa Lu

Yu-Jen Cheng

Chang-Chia Huang

Kuan-Hung Chen

An electrical connection structure includes a dielectric layer stack of a plurality of dielectric layers including a first dielectric layer as an uppermost layer, and a second dielectric layer under the first dielectric layer, a plurality of metal layers in the plurality of dielectric layers, a via stack in the plurality of dielectric layers that connects the plurality of metal layers, an upper metal layer on the dielectric layer stack over the via stack, and an upper dielectric layer on the dielectric layer stack and including an upper dielectric layer opening over the upper metal layer and the via stack. A number of first vias in the first dielectric layer, may be less than or equal to a number of second vias in the second dielectric layer, and the number of second vias in the second dielectric layer may be less than or equal to 3.

Stacking via configuration for advanced silicon node products and methods for forming the same

A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Heterogeneous bonding structure and method forming same

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

MIMcap corner structures in the keep-out zones of a semiconductor die and methods of forming the same

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Packages with stacked dies and methods of forming the same

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Bonding structures in semiconductor packaged device and method of forming same

A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

Programmable inductor and methods of manufacture

A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Metal bumps and method forming same

A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

Process for tuning via profile in dielectric material

A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

Seal ring structure with zigzag patterns and method forming same

Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Package structure

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.

Semiconductor device structure with magnetic element

A semiconductor package structure includes first via structures formed through a core substrate. The structure also includes an interposer embedded in the core substrate between the first via structures. The interposer includes second via structures formed through an interposer substrate. The structure also includes a first redistribution layer structure formed over the core substrate. The structure also includes a second redistribution layer structure formed under the core substrate. The structure also includes a first encapsulating layer formed between a sidewall of the interposer and a sidewall of the core substrate.

Semiconductor package structure and method for forming semiconductor package structure

A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Packages including multiple encapsulated substrate blocks and overlapping redistribution structures

A semiconductor device including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure and a second connector structure is provided. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

Semiconductor device

A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

Semiconductor die

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Sinpu, Taiwan

Mirng-Ji Lii