Infineon Technologies Austria Ag

Minghao Jin

Oliver Blank

Rudolf Rothmaler

Franz Hirler

Martin Henning Vielemeyer

Li Juin Yip

Johannes Baumgartl

Joerg Ortner

Christof Altstaetter

Quaglino Roberto

A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Method of manufacturing a semiconductor device having a charge compensation region underneath a gate trench

A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.

Semiconductor device comprising trench structures

A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.

Electrode-aligned selective epitaxy method for vertical power devices

A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Semiconductor device with charge compensation region underneath gate trench

A method for operating a circuit includes providing a three terminal main transistor and a four terminal sense transistor having a field plate. The method includes simultaneously applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor, and applying a field plate pulse on a field plate of the sense transistor. The field plate pulse is synchronous and in phase with the gate pulse.

Current sensors and methods of improving accuracy thereof

A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends into the semiconductor body from the first surface and includes first and second sidewalls extending across the semiconductor body in a lateral direction that is parallel to the first surface. A field electrode is arranged in first trench and electrically insulated from the semiconductor body by a field dielectric. A first gate electrode is arranged in the first trench. The first gate electrode is electrically insulated from the field electrode by the field dielectric and is electrically insulated from the semiconductor body by a first gate oxide. The first gate electrode includes widened and tapered portions that are continuously connected and adjacent to one another in the lateral direction. The first gate oxide forms a non-perpendicular angle with the first sidewall in the lateral direction.

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Villach, Austria

Minghao Jin