Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Yi Lee

Hung-Jen Liao

Li-Chun Tien

Cheng Hung Lee

Chi-Hung Liao

Kuo-Hua Pan

Hong-Chen Cheng

Jung-Hsuan Chen

Yen-Huei Chen

Chia-En Huang

Hidehiro Fujiwara

Kao-Cheng Lin

Fu-An Wu

Jung-Ping Yang

Cheng-Hung Lee

Yao-Sheng Huang

Tien-Chen Hu

I-Han Huang

Ying-Hsiang Chen

Yan-Wei Tien

Yao-Wei Tien

Hui-Lun Chen

Chien-Hsien Lee

Tsen-Hsing Yi

The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.

System and method for defect analysis of a substrate

A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.

Memory with bit cell header transistor

A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern. The second interconnection layout pattern overlaps the isolation region.

Layout design for manufacturing a memory cell

A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

Memory edge cell

A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.

Mixed-mode process

The present invention discloses an apparatus and method for cleaning an exhaust conduit that has chemical substances deposited on its inside wall by utilizing a shaft that has a plurality of scraping elements mounted thereto capable of making vertically or radially oscillating motions inside the exhaust conduit such that the chemical substances can be dislodged from the inside wall and the exhaust conduit can be effectively cleaned. The apparatus may optionally include fluid nozzles provided in the shaft for dispensing a cleaning fluid during the cleaning process to further enhance the efficiency. The apparatus may further include a vacuum device for effectively removing the debris dislodged from the inside wall during such cleaning process.

Apparatus and method for cleaning a conduit

A wafer mounting plate for mounting a wafer in a chemical mechanical polishing process and a method for using the wafer mounting plate are disclosed. The novel mounting plate for a silicon wafer is designed to incorporate a concave mounting surface for contacting a wafer with a flexible membrane layer thereinbetween. The wafer mounting plate is further provided with a plurality of apertures therethrough for use as vacuum passageways for picking up a wafer through a perforated or breathable membrane layer. The concave surface of the wafer mounting plate that contacts the wafer substantially eliminates stress concentration problems imposed on the wafer by conventional wafer mounting plates. The present invention novel apparatus therefore not only eliminates the edge defect problem that is normally associated with the conventional mounting plates, but further solves the wafer breakage problem frequently caused by stress concentration imposed on the wafer by a bumper ring. The present invention further discloses a method for using a wafer mounting plate during a chemical mechanical polishing process which does not create stress concentration on the wafer and therefore provides a safe and reliable method for loading/unloading a wafer from a load cup, or chucking or dechucking a wafer from a polishing pad.

Wafer mounting plate for a polishing apparatus and method of using

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Zhudong, Taiwan

Ming-Yi Lee