Texas Instruments Corporation

Ming Yang

Abbas Ali

Takayuki Niuya

Freidoon Mehrad

Lancy Y Tsung

Vikram N Doshi

Thomas M Ambrose

Fred D Fishburn

Jim Huang

Tom Lassister

Masahiro Kaida

Jiaming Huang

The invention describes a method for forming a dual damascene structure. An etch stop layer () is formed on a dielectric layer (). A second dielectric layer () is formed on the etch stop layer () and an ARC layer () is formed the second dielectric layer. A first trench () and a second trench () are then simultaneously formed in the first and second dielectric layers () and () respectively.

Process for forming a dual damascene structure

A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is nearly removed, a drop in voltage indicates thinning of the film which detects endpoint for etching before optical emission techniques. The voltage drop is measured across resistors within the matching network.

Endpoint control for small open area by RF source parameter Vdc

A method of forming a semiconductor component having a conductive line ( ) and a silicide region ( ) that crosses a trench ( ). The method involves forming nitride sidewalls ( ) to protect the stack during the silicidation process.

Method to salicide source-line in flash memory with STI

The invention describes a method for forming a dual damascene structure. An etch stop layer ( ) is formed on a dielectric layer ( ). A second dielectric layer ( ) is formed on the etch stop layer ( ) and an ARC layer ( ) is formed the second dielectric layer. A first trench ( ) and a second trench ( ) are then simultaneously formed in the first and second dielectric layers ( ) and ( ) respectively.

A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (,) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (,) are disposed. A silicon nitride layer (,) is in place below the BPSG layer (,), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (,) during high temperature processes such as reflow and densification of the BPSG layer (,) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (,) and the silicon nitride layer (,) using a two-step etch process. The first etch selectively etches silicon dioxide relative to silicon nitride, and thus stops on silicon nitride layer (,); besides serving as an etch stop, silicon nitride layer (,) protects underlying active regions (,) from damage that may be caused by ionized oxygen released during oxide etch. A brief nitride etch is then used to clear silicon nitride layer (,), without damaging comer locations (NC) of the sidewall structures (,).

Silicon nitride dopant diffusion barrier in integrated circuits

The sidewall nitride etch is modified to leave a thin layer of nitride covering the silicon in a DRAM array. The nitride layer prevents damage to the silicon and improves the integrity and refresh time of the array.

Process sequence to improve DRAM data retention

A method for etching a semiconductor device (10) having BARC layer (22) and nitride layer (20) includes etching BARC layer (22) until reaching a first set point in the fabrication reaction chamber and then etching nitride layer (20) in-situ the fabrication reaction chamber immediately following etching BARC layer (22).

In-situ barc and nitride etch process

An integrated circuit includes a conductive structure (66) is formed with a top layer of silicon nitride (62) and silicon nitride (70) sidewalls on a semiconductor substrate. The layer of silicon nitride (70) covering the sidewalls of the conductive structure (66) intersect with the layer of silicon nitride on top of the conductive structure with a relatively square shoulder. A subsequently deposited conductor makes contact with the surface of the semiconductor substrate (56) without shorting to the conductive structure (66) on the semiconductor substrate.

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Richardson, TX, United States of America

Ming Yang