Sandisk Technologies Inc.

Delta Electronics (Shanghai) Co., Ltd

Fudan University

Basf Coatings Gmbh

Ming Wang

Liang Li

Jiahui Yuan

Wei Zhang

Hong Li

Jian-Ping Ying

Teng Liu

Anubhav Khandelwal

Hong-Jian Gan

Tao Jiang

Ke Zhang

Bing Zhang

Cathrin Corten

Yichen Wang

Chao Xu

Xuan Tian

Jianxing Dong

Na Liu

Li-Feng Qiao

Stefan Hirsemann

Yingying Zhu

Jian-Gang Huang

Xiaohu Li

Mushtaq Patel

Shrirang Hindalekar

Jie Cao

Rahul Mulay

Jing Yin

Sixiang Zhao

Ling Yu Sui

Qin Yuan Chen

Chun Yang Li

Yuan Yuan Song

To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.

Adaptive erase pulse to improve memory cell endurance and erase time in non-volatile memory

Technology for zoned read parameters. The read parameters may include read reference levels and/or offsets applied to base read reference levels. The memory system may assign memory cells located in a region (e.g., block) into zones based on a ranking of a target read level for each set of memory cells in the region. The memory system may assign word lines in a block into zones based on a ranking of a target read voltage and/or target read voltage offset for each word line. The memory system may read each particular set of memory cells (e.g., word line in the block) using a representative read voltage for the zone into which the particular word line is assigned.

Read parameter zoning

An apparatus includes a memory structure including non-volatile memory cells, and a control circuit coupled to the memory cell. The control circuit configured to first read a block of non-volatile memory cells using a first plurality of read levels, determine that the first read fails to successfully read the block of non-volatile memory cells, second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels, determine that the second read successfully reads the block of non-volatile memory cells, estimate that the first read failed because of data retention or read disturb, and erase and re-write data to the block of non-volatile memory cells.

Apparatus and methods for read retry with conditional data refresh

A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Non-volatile memory with decline state operation

A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage ('GIDL') generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.

Non-volatile memory with sub-block programming

The present invention relates to a self-assembled avalanche-responsive device and the preparation and application thereof. The responsive device is prepared through the following process: (1) taking an insulating substrate and depositing metal electrodes on both ends of an upper surface of the insulating substrate; (2) taking a nano-conductive filler and an interface modifier, adding the nano-conductive filler and the interface modifier to an elastomer matrix solution, performing stirring and mixing, and performing ultrasonic dispersion to obtain a conductive polymer solution; and (3) spin-coating the obtained conductive polymer solution onto a silicon substrate through a spin-coating process to cover terminals of the two metal electrodes provided opposite to each other; and performing drying, so as to obtain a responsive layer, so that the process is completed.

Self-assembled avalanche-responsive device and preparation thereof

Technology to prevent over-erase in NAND memory. Each bit line involved in erase is connected to multiple NAND strings. Erase verify of each NAND string is performed at a final target level and a level that is somewhat higher than the final target level. Bit lines are placed into three groups based on the erase status of the NAND strings connected to the bit line. The erase voltage applied to the bit lines in the next erase loop depends on the group in which the bit line was placed.

Smart erase inhibit

Embodiments disclosed herein are directed to a memory device, comprising control circuitry configured to: perform a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for a first string; perform a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string; and perform the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for a second string, wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

Enhanced bit error rate estimation scan process

Technology is disclosed herein for simultaneous lower tail program verify with upper tail verify. The memory system may apply a reference voltage to a word line following applying a program voltage to the word line. The memory system senses the first set of memory cells targeted for a first data state and the second set of memory cells targeted for a second data state. The memory system determines whether memory cells in the first set have a Vt greater than a maximum target Vt for the first data state based on the sensing of the first set of memory cells. The memory system also determines whether memory cells in the second set have a Vt less than a minimum target Vt for the second data state based on the sensing of the second set of memory cells.

Simultaneous lower tail verify with upper tail verify

Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Non-volatile memory bitmap for garbage collection

An electrical system includes a first conduction terminal, a second conduction terminal, N power units and N supporting devices. The N power units are electrically connected between the first conduction terminal and the second conduction terminal in series, and N is an integer greater than or equal to 2. Each of the N supporting devices includes a conductive part and a support part. Each of the N power units is disposed on the corresponding conductive part. The conductive part is electrically connected with a power terminal of one of the N power units or electrically connected with a reference potential of the electrical system. The support part is connected between the corresponding conductive part and a ground potential.

Electrical system and supporting device thereof

A non-volatile memory system is configured to permanently erase a single file from a block of non-volatile memory cells. That block is storing programmed data including the single file to be erased and other programmed data. The single file is erased from the block such that the other programmed data in the block is not moved or otherwise disturbed.

Non-volatile memory with secure erase

The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

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Shanghai, China

Ming Wang