United Microelectronics Corp.

United Semiconductor Corp.

Ming-Tsung Liu

Tsung-Yuan Hung

Tsun-Tsai Chang

Water Lur

Bill Y Hsu

Der Yuan Wu

D Y Wu

Jeffrey Wang

Wen Yang Chen

Vicent Liu

A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer first formed over a semiconductor substrate. A trench is formed in the substrate. A first insulating layer is formed over the substrate. The surface of the first insulating layer within the trench is be between the hard masking layer surface and the semiconductor substrate surface. An insulating cap layer is formed over the first insulating layer with a hardness at least about as large as the hard masking layer. A second insulating layer is formed over the insulating cap layer. A chemical mechanical polishing (CMP) process is performed, using the hard masking layer as a polishing stop, to planarize over the substrate. A process of dipping the substrate into a HF acid solution is performed to remove the hard masking layer and the pad oxide layer, in which the process also simultaneously removes the remaining second insulating layer and the remaining insulating cap layer. The STI structure is accomplished with a significant avoidance of dishing and microscratch.

Method for fabricating a shallow trench isolation structure using

A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Method of etching metal with increased etching selectivity

A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect layer. A silicide layer is formed on the sidewall of the interconnect layer. The silicide layer connects a buried contact region with the interconnect layer to make electrical contact between the interconnect layer and a source/drain region.

Method of fabricating a buried contact structure for SRAM

A process for coding and code marking a read-only memory device makes use of a buffer layer, such as silicon nitrides (Si.sub.3 N.sub.4) or silicon oxynitrides (SiN.sub.x O.sub.y), to form a code mark therein. Owing to the etching selectivity between the buffer layer and an underlying layer, for example, silicon oxides, the programmed region not covered by the word lines will not suffer from etching damage while forming the code mark. Therefore, the coding and code marking process can employ the same mask layer, but without the need for two different photomasking procedures to implement code programming and identification code marking.

Process for coding and code marking read-only memory

A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.

Spin-on-glass planarization process with ion implantation

In the fabrication of VLSI circuits, the diffusion barrier layer on the pad areas are removed prior to the formation of metal layer. Metal layer on the pad areas are thus directly contact with the underlying SiO.sub.2 layer, thereby improving the pad bonding yield.

Growing community of inventors

Hsinchu, Taiwan

Ming-Tsung Liu