Sandisk Technologies Inc.

Shanghai Huali Integrated Circuit Corporation

Ming Tian

Henry Chien

Atsushi Suyama

Dana Lee

Henry Chin

Vinod Robert Purayath

Takashi Whitney Orimoto

Raghuveer S Makala

Johann Alsmeier

James K Kai

Jayavel Pachamuthu

Tuan Duc Pham

Yao-Sheng Lee

Nan Li

Jongsun Sel

Hiroaki Iuchi

Tianpeng Guan

Zhonghua Li

Masanori Terahara

Jianghua Leng

Hirofumi Watatani

Hitomi Fujimoto

Daisuke Maekawa

Yufeng Chen

The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

Method for manufacturing FDSOI

Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation.

Air gap isolation in non-volatile memory using sacrificial films

A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

Method of forming an active area with floating gate negative offset profile in FG NAND memory

A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.

Memory cell floating gate replacement

Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

P-type control gate in non-volatile storage

P-type control gate in non-volatile storage and methods for forming same

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Yokkaichi, Japan

Ming Tian