Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Semiconductor Engineering, Inc.

Ming-Shuoh Liang

Jye-Yen Cheng

Chen-Yu Shyu

Tai-Chun Huang

Chih-Hsiang Yao

Chin-Chiu Hsia

Wen-Kai Wan

Chih-Cherng Jeng

Kuan-Shou Chi

Hung-Nan Chen

Sung-Ching Hung

Simon Lee

An interconnect structure includes a damascene structure, an inter-metal dielectric (IMD), a dielectric block and a metal via. The inter-metal dielectric layer is over the damascene structure. The dielectric block is embedded in the IMD layer and has a different etch selectivity than the IMD layer. The metal via is in the IMD layer and through the dielectric block to electrically connect the damascene structure.

Interconnect structure and method of forming the same

Methods of fabricating an integrated circuit device are provided. The method includes depositing a dielectric layer and a first hard mask layer in sequence over a substrate. The method also includes forming a patterned second hard mask on the first hard mask layer, and forming a third hard mask portion in an opening of the patterned second hard mask. The method further includes removing the patterned second hard mask to leave the third hard mask portion on the first hard mask layer, and etching the first hard mask layer to form a patterned first hard mask. In addition, the method includes etching the dielectric layer by using the patterned first hard mask as an etching mask to form trenches in the dielectric layer, and filling the trenches with a conductive material to form conductive lines.

Methods of fabricating integrated circuit devices having reduced line end spaces

A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

Seal ring structure for integrated circuit chips

A testing module for testing the strength of the welding area on a PCB is disclosed. The testing module has a plurality of first plates each provided with a plurality of pressing plates adjustably mounted thereon and a plurality of second plates each provided with a plurality of supporting plates securely mounted thereon. Each of the pressing plates are located at the center of two adjacent supporting plates, such that a plurality of PCBs are able to be tested for the strength of the welding area at a time.

Testing module for testing the strength of the welding area on a PCB

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Kaohsiung, Taiwan

Ming-Shuoh Liang