Winbond Electronics Corporation

Ming-Lun Chang

Wei-Fan Chen

Wen-Pin Chang

Wen-Shiang Liao

The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before carrying on the self-aligned silicidation. The implanted ion of the present invention, such as fluorine, chlorine, bromine, iodine, boron and trifluroborane, will react with the silicon on the surface of the gate structure and the silicon substrate and a barrier effect will be formed during silicidation. Therefore, a spike phenomenon because of the penetration of cobalt or the cobalt silicide into the gate structure or the source/drain regions is prevented. The junction leakage current and the breakdown voltage of the metal oxide semiconductor are avoided.

Method for forming a self-aligned silicide of a metal oxide semiconductor

The present invention provides a method for making the bottom electrode of a buried capacitor, which is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si glass remaining in non-bottom electrode region from driving into the substrate during annealing, thus non-desired diffusing region connecting to the bottom electrode will be generated. Consequently, the leakage current existing in conventional buried capacitor will be effectively reduced according to the method of this present invention.

Method for making the bottom electrode of a capacitor

A method for forming a metal line structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a metallic layer and an insulating layer over the substrate. Next, photolithographic and etching processes are performed to create a pattern on the insulating layer exposing portions of the metallic layer and forming insulating lines. Then, spacers are formed on the sidewalls of the insulating lines. Thereafter, the metal layer is etched using the insulating lines and the spacers as masks, and the substrate as an etching stop layer. The metal etching also removes the insulating lines. Thus, the top surface of the metallic layer is exposed and the metal line structure that has the characteristic sloping sidewalls of this invention is formed. These outward sloping sidewalls of the metal lines form slanted edges with the semiconductor substrate, and provide a good step coverage for subsequently deposited layer.

Metal line structure and method of manufacturing the same

According to the manufacturing method for capacitors, which characterizes in using trench technique that is usually used in DRAM processes to form multiple bottom electrodes of the capacitor in a trench's sidewall, then increase the whole surface of the capacitor and enhance the charge stored in the electrodes. The capacitance of the capacitor manufactured by this invention is double that manufactured by conventional methods. In addition, the structure of the capacitor manufactured by this invention is multiple stages; therefor the depth of trenches is less than that manufactured by conventional methods. This manufacturing method according to the invention improves many difficulties existing in conventional processes.

Methods for manufacturing DRAM capacitors

A polysilicon load structure and its manufacturing method for static random access memory, comprising the steps of first providing a semiconductor substrate, and then forming a first insulating layer over the substrate. Next, a trench is etched out from the insulating layer forming a step structure. Thereafter, a polysilicon layer is formed over the first insulating layer, and then a global ion implantation operation is performed. Next, a photoresist layer is formed over the polysilicon layer, and then a connector pattern is defined using a microlithographic process. Thereafter, the polysilicon layer is anisotropically etched to form a spacer on the sidewall of the trench. Subsequently, a second ion implantation is performed to adjust the resistance of the connector. Finally, microlithographic and etching processes are used to remove the unwanted portions of the polysilicon spacer and exposing the polysilicon spacer structure and the polysilicon connector structure.

Structure of polysilicon load for static random access memory

A self-aligned via structure and its method of manufacture comprising the steps of providing a semiconductor substrate, and then sequentially forming a conductive layer and a dielectric layer over the substrate. Next, a hollow cavity is etched out in the dielectric layer. Then, a photolithographic process is performed by coating a photoresist layer over the dielectric layer and the cavity, followed by creating a pattern of desired conductive lines so that portions of the photoresist layer overlaps with the cavity. Subsequently, using the photoresist layer as a mask, the dielectric layer and the conductive layer are etched to form a multiple of conductive lines. Thereafter, a selective liquid phase deposition is performed to deposit an oxide layer over the substrate in regions outside the photoresist-occupied regions. Finally, the photoresist layer is removed to form the via structure of this invention in the oxide layer.

Self-aligned via structure and method of manufacture

High-resistance polysilicon layers applied in 4T SRAM memory cells serving as loads, are manufactured by a simple method according to the invention. In the small-scale 4T SRAM memory cell process, it is not possible to fabricate traditional polysilicon loads manufactured by the prior art with a desired high degree of resistance. As a result, the miniaturization of 4T SRAM memory cells has been limited. However, in the method according to the invention, the lengths of polysilicon loads are greatly increased without increasing the sizes of corresponding memory cells, thereby efficiently increasing the resistance of the polysilicon loads. Therefore, this method according to invention can completely eliminate any limitation to the small-scale 4T SRAM memory cell process caused by the manufacture of the polysilicon loads as described above.

Method and structure for manufacturing high-resistance polysilicon loads

A method of fabricating a semiconductor device. The procedure of fabricating process is performed inversely as the conventional method. Less numbers of photolithography process is performed with the application of selective liquid phase deposition.

Method of fabricating semiconductor

A method for fabricating a load device on an SRAM is provided which substantially increases the effective length of its load device without increasing the cell size. This method includes the steps of: (1) depositing an interpoly dielectric layer on a wafer surface; (2) depositing a first oxide layer on the interpoly dielectric layer; (3) using a photography technique to form at least one first oxide stripe from the interpoly dielectric layer in a direction perpendicular to the direction of the polysilicon load; (4) depositing a second oxide layer on and around the first oxide stripe, then etching back the second oxide layer to form a second oxide spacer on the sidewalls of the first oxide stripe; (5) using a selective etching technique to etch the first oxide stripe, leaving the second oxide spacer on the wafer surface; (6) using a photolithography technique and masked dopant-implantation to form a polysilicon layer on the surface, the polysilicon layer contains a highly doped connector region and an undoped or lightly doped load region. The load region is formed in a direction perpendicular to the second oxide stripe and conformed to the profile of the second oxide stripe so as to assume a three-dimensional heaved structure on top thereof and provide an enhanced effective length.

Method for preparing polysilicon load

Manufacturing method of polysilicon load for static random access memory

A method of planarizing an inter-metal dielectric layer includes providing a semiconductor substrate having a component layer formed thereon; and forming a metallic layer over the component layer. Then, portions of the metallic layer are etched to form metal pads on the metallic layer surface. Next, the metallic layer is patterned and portions of the metallic layer are etched to form a plurality of metal lines and trenches between the metal lines. Subsequently, a first oxide layer is deposited over the metal lines and the trenches, and then a spin on glass layer is formed over the first oxide layer, filling up the trenches. Thereafter, portions of the spin on glass layer are etched back to expose the metal pad and form a residual spin on glass layer, and then a second oxide layer is formed over the metal pad, the residual spin on glass layer and the first oxide layer. Portions of the second oxide layer are etched to form an opening in the second oxide layer that corresponds to the metal pad location. The opening is subsequently used to form a via plug.

Method of improving the planarizaton of an inter-metal dielectric layer

A process for forming self-aligned silicide which is suitable for high-integrity processes after applying planarization technology. The present invention can protect the self-aligned silicide from being over-etched during subsequent contact etching process by means of forming a thicker silicide layer on the positions with shallower contact windows. At first, a polysilicon layer and a titanium layer are suquentially formed on a substrate having a field oxide, and defined to form a gate in an active region and a polysilicon line on the field oxide with titanium thereon. Then, impurities are implanted to form an LDD, an insulating layer is deposited and etched back to form a sidewall spacer of the gate and polysilicon line, and source/ drain regions are formed on the sides of the gate. After source/drain regions are formed, another titanium layer is formed so that titanium on the gate and polysilicon line is thicker than that on other regions. Accordingly, self-aligned silicide can be achieved by activating the reaction of titanium and silicon and selectively removing unreacted titanium.

Growing community of inventors

Hsinchu, Taiwan

Ming-Lun Chang