Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Kai Liu

Kai-Chiang Wu

Yen-Ping Wang

Shih-Wei Liang

Ching-Feng Yang

Chun-Lin Lu

Chia-Chun Miao

Han-Ping Pu

Ting-Chu Ko

Yung-Ping Chiang

Yu-Sheng Hsieh

Chang-Wen Huang

Ching-Yu Huang

Hsien-Wei Chen

Chuei-Tang Wang

Hao-Yi Tsai

Chao-Wen Shih

Hsin-Yu Pan

Chen-Hua Douglas Yu

Chung-Shi Liu

Wei-Ting Lin

Vincent Chen

Tzu-Chun Tang

Hung-Jen Lin

Shou Zen Chang

Chung-Hao Tsai

Chun-Hung Lin

Yu-Feng Chen

Shou-Zen Chang

Lipu Kris Chuang

Mirng-Ji Lii

Wei-Hung Lin

Yu-Peng Tsai

Shih-wei Liang

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Stacked memory cube with integrated thermal path for enhanced heat dissipation

Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Semiconductor packages and methods of forming the same

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

Memory device and manufacturing method thereof

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Integrated fan-out packages and methods of forming the same

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Methods of manufacturing a semiconductor device including a joint adjacent to a post

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

Methods and apparatus for package on package devices

A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.

Semiconductor device

Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

Package structure and method of manufacturing the same

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

Surface mounting semiconductor components

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.

Interconnection structure including a metal post encapsulated by a joint material having concave outer surface

A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

Method for singulating packaged integrated circuits and resulting structures

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.

Growing community of inventors

Taipei, Taiwan

Ming-Kai Liu