Industrial Technology Research Institute

Ming-Ji Dai

Chun-Kai Liu

Ra-Min Tain

Chih-Kuang Yu

Heng-Chieh Chien

John H Lau

Chih-Ming Shen

Yu-Lin Chao

Sheng-Tsai Wu

Ming-Che Hsieh

Ming-Kaan Liang

Li-Ling Liao

Cheng-Ta Ko

Shih-Hsien Wu

Sheng-Liang Li

Shyh-Shyuan Sheu

Ming-Te Lin

Chih-Sheng Lin

Chih-Chung Chiu

Shyi-Ching Liau

Wei-Kuo Han

Chin-Hung Wang

Kuang-Yu Tai

Jing-Yi Huang

Chih-Ming Tzeng

I-Nan Lin

Wei Yu Li

Chih-Yuan Cheng

Zhi-Cheng Hsiao

An-Chun Luo

Suh-Yun Feng

Huey-Lin Hsieh

Yon-Hua Tzeng

Jui-Feng Hung

Yu-Shan Deng

Tsung-Chieh Cheng

Chung-Yen Hsu

Ker-Win Wang

Yen-Lin Tzeng

Yan-Bo Lin

A board defect filtering method is provided. The method includes: receiving a defect list; obtaining a plurality of defect images of a plurality of defect records on the defect list; receiving a circuit layout image; analyzing a defect location of a first defect image of the plurality of defect images according to the circuit layout image; cropping the first defect image to obtain a first cropped defect image according to the defect location; inputting the first cropping defect image to a defect classifying model; and determining whether the first defect image is a qualified product image or not according to an output result of the defect classifying model.

Board defect filtering method based on defect list and circuit layout image and device thereof and computer-readable recording medium

A chip temperature computation method and a chip temperature computation device are provided. The chip temperature computation method includes: computing an upper layer thermal resistance and a lower layer thermal resistance of a chip, computing a total thermal resistance of the chip, and computing a temperature of the chip according to the total thermal resistance.

Chip temperature computation method and chip temperature computation device

Provided is a roller with pressure sensor. The roller includes a pressure sensor mounted to the roller. The pressure sensor includes a plurality of pressure sensing units distributed on a thin film. The pressure sensing units are electrically connected to each other with a metal wire but not in contact with each other. Also provided is a roll-to-roll device, which includes a roller mechanism and a pressure sensor.

Roller with pressure sensor and R to R device

An intelligent diagnosis system for a power module. The system includes a power module, a hardware checking module and a diagnostic module. The power module has a temperature sensing element for obtaining a temperature difference between a starting minimum temperature and a current temperature. The hardware checking module has a current sensing element, a voltage sensing element and a magnetic coupling closed loop detection element for obtaining the current, the output voltage and the input voltage of the power module, and the hardware loop status, respectively. The diagnostic module calculates the number of cycles that have been operated, a measured impedance and an instantaneous power based on those measurement results, and calculating a risk index based on the number of cycles that have been operated, the temperature difference, the measured impedance, the instantaneous power and the hardware loop status, thereby determining the accumulation of the abnormality index record.

Intelligent diagnosis system for power module and method thereof

A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.

Measurement method, measurement apparatus, and computer program product

An encapsulation of backside illumination photosensitive device including a circuit sub-mount, a backside illumination photosensitive device, a plurality of conductive terminals, and a heat dissipation structure is provided. The backside illumination photosensitive device includes an interconnection layer and a photosensitive device array, wherein the interconnection layer is located on the circuit sub-mount, and between the photosensitive device array and the circuit sub-mount. The conductive terminals are located between the interconnection layer and the circuit sub-mount to electrically connect the interconnection layer and the circuit sub-mount. The heat dissipation structure is located under the interconnection layer, and the heat dissipation structure and the photosensitive device array are respectively located at two opposite sides of the interconnection layer.

Encapsulation of backside illumination photosensitive device

A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

Semiconductor device

A thermoelectric apparatus includes a first and a second assemblies, at least a first and a second heat conductors. The first assembly includes a first and a second substrates, and several first thermoelectric material sets disposed between the first and second substrates. The first substrate has at least a first through hole. The second assembly includes a third and a fourth substrates, and several second thermoelectric material sets disposed between the third and fourth substrates. The fourth substrate has at least a second through hole. Each of the first and second thermoelectric material sets has a p-type and an n-type thermoelectric element. The first and second heat conductors respectively penetrate the first and second through holes. Two ends of the first heat conductor respectively connect the second and fourth substrates, while two ends of the second heat conductor respectively connect the first and third substrates.

Thermoelectric apparatus and method of fabricating the same

A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.

Self-assembly apparatus, device self-assembling method, and method of assembling thermoelectric devices

A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. A chemical vapor deposition (CVD) diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the CVD diamond film. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Heat dissipation structure for electronic device and fabrication method thereof

An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.

Electronic device packaging structure

A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Chip stacking structure and fabricating method of the chip stacking structure

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Measuring apparatus that includes a chip with a through silicon via, a heater having plural switches, and a stress sensor

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Growing community of inventors

Hsinchu, Taiwan

Ming-Ji Dai