Texas Instruments Corporation

Ming J Hwang

Chih-Chen Cho

Wei-Yung Hsu

Gonzalo Amador

Duane E Carter

Jiong-Ping Lu

Tsuyoshi Tamaru

William R McKee

Leslie Edward Stark

Dirk N Anderson

Sunil V Hattangady

Jeffrey A McKee

Shintaro Aoyama

Paul Tiner

Lobo Wang

Tadashi Terasaki

Keizo Hosoda

Lee M Loewenstein

Darvin R Edwards

Robert Yung-Hsi Tsu

Thomas E Tang

Takayuki Niuya

Jorge A Kittl

Steve S Huang

Paul S Blanton

Peter S Ying

Rachelle J Bienstock

Jing Shing Shu

Steven K Groothuis

Robert C Baumann

Boyang Lin

Kyung-Ho Park

Hun-Lian Tsai

Harold J Dowell

Gail Heinen

Leo Rimpillo

Toyotaro Horiuchi

Song C Park

Jiong Ping Lu

Dick N Anderson

An embodiment of the instant invention is a method of oxidizing a first feature (feature and/or feature of FIG. and feature of FIG. ) while leaving a second feature substantially unoxidized (features and of FIG. and features and of FIG. ), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O , N O, CO , H O, and any combination thereof, and the hydrogen-containing gas is comprised of H . The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Selective oxidation for semiconductor device fabrication

A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

Method for reducing by-product deposition in wafer processing equipment

A method of forming an ultra-thin gate oxide ( ) for a field effect transistor ( ). The gate oxide ( ) is formed by combining an oxidizing agent (e.g., N O, CO ) with an etching agent (e.g., H ) and adjusting the partial pressures to controllably grow a thin (&tilde;12 Angstroms) high quality oxide ( ).

Controllable oxidation technique for the formation of high-quality ultra-thin gate oxide using carbon dioxide as the oxidizing agent

Contacts for an electronic device are formed by providing a substrate ( ) that has at least two access line structures ( ) for a memory array ( ) and a periphery structure ( ) for a peripheral circuit ( ) to the memory array ( ). A first insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), and the periphery structure ( ). A contact area of the periphery structure ( ) is exposed through the first insulative layer ( ) while maintaining the first insulative layer ( ) over at least a contact overlap portion ( ) of the access line structures ( ). A second insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), the periphery structure ( ), and the first insulative layer ( ). A self-aligned contact hole ( ) overlapping the contact overlap portion ( ) of the access line structures ( ) and a periphery contact hole ( ) overlapping the contact area ( ) of the periphery structure ( ) are formed through the second insulative layer ( ) with a same mask ( ). A self-aligned contact ( ) is formed in the self-aligned contact hole ( ) and a periphery contact ( ) is formed in the periphery contact hole ( ).

Method for forming memory array and periphery contacts using a same mask

Controllable oxidation technique for high quality ultrathin gate oxide formation

A chemical mechanical polishing machine with ultrasonic vibration is disclosed. The chemical mechanical polishing machine (,) includes a movable abrasive surface (,). A wafer holder (,) holds a wafer (,) in contact with the abrasive surface (,), and a vibration generator (,) vibrates the wafer (,) during polishing. The ultrasonic vibration agitates the slurry and provides an additional degree of motion between the wafer and the abrasive surface, thereby increasing the speed and uniformity of the polishing.

Chemical mechanical polishing machine with ultrasonic vibration and method

A method for protecting metal (,) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (,), smile oxidation, and sidewall (,) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (,) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.

Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing

A thermal neutron shield (,) for integrated circuits (,) deters absorption of thermal neutrons by circuit constituents to form unstable isotopes with subsequent decay which generates bursts of charge which may upset of stored charge and create soft errors. The shielding may be either at the integrated circuit level (such as a layer on insulation or in the filler of plastic packaging material) or at the board level (such as a filler or film on a container wall).

Thermal neutron shielded integrated circuits

A method and apparatus for selectively heating a structure capable of absorbing heat radiations in the 0.5 to 2 micron range relative to an adjacent structure wherein a first structure capable of absorbing heat radiations in the 0.5 to 2 micron range is disposed adjacent a second structure much less capable of absorbing heat radiations in the 0.5 to 2 micron range. An unfocused heat source which provides a major portion of its heat energy in the range of from about 0.5&mgr; to about 2&mgr; relative to heat energy above 2&mgr; and below 0.5 micron directs heat concurrently to the first and second structures to heat the first structure to a temperature sufficiently high and much higher then the second structure to permit a predetermined function to be performed in conjunction with the first structure while maintaining the second structure below a predetermined temperature. The function is then performed. The heat source preferably comprises an unfocused tungsten halogen lamp.

Rapid and selective heating method in integrated circuit package assembly by means of tungsten halogen light source

Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (,) over an oxidizable section (,) of the semiconductor device. The protective cover (,) is operable to at least inhibit oxidation of the oxidizable section (,). While the oxidizable section (,) is covered, an oxide structure (,) is formed. The oxide structure (,) is operable to at least ameliorate etch damage to the semiconductor device.

Post-etch treatment of a semiconductor device

A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.

Method for a semiconductor device having reduced contact resistance and leakage

A cost-effective method for fabricating MIM capacitors (,). After metal (,) deposition, the metal oxide (,) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (,) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.

Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication

A process for forming a W-poly gate stack (,) comprising the steps of: (1) deposition of doped polysilicon (,) on a thin dielectric layer (,) covered substrate (,), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (,) and to remove excess nitrogen and (4) deposition of W layer (,). The stack layers are then etched to form the gate electrode (,).

CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes

A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (,) over a gate oxide (,) followed by protection of the polysilicon (,) with a sacrificial material (,), is disclosed. Gate sidewalls (,) are created to protect the sides of the polysilicon (,) and the sacrificial material (,), followed by stripped the sacrificial material (,) to expose the top surface of the polysilicon (,). Next, a diffusion barrier (,) is deposited over the exposed polysilicon (,) and a metal layer (,) is selectively grown on the diffusion barrier (,) to form a gate contact and conductor. Finally, a dielectric layer (,) is deposited over the selectively grown metal layer (,), the sidewalls (,) and the gate oxide (,).

Low resistivity poly-silicon gate produced by selective metal growth

Growing community of inventors

Dallas, TX, United States of America

Ming J Hwang