Etron Technology, Inc.

Piecemakers Technology, Inc.

Moai Electronics Corporation

Piecemakers Technology, Incorporation

Ming-Hung Wang

Tah-Kang Joseph Ting

Gyh-Bin Wang

Chun Shiah

Bor-Doou Rong

Chun-Peng Wu

Jen-Shou Hsu

Peng-Fei Lin

Li-Chin Tien

Ming-Chi Lin

Chun-Chi Shen

Jen-Shoe Hsu

Cheng-En Shieh

A method for handling defective regular local wordlines in a memory module is provided. The method includes: providing one or more sets of spare local wordlines; utilizing a spare control logic to generate a plurality of match signals by comparing an input address with a plurality of fail addresses; utilizing the spare control logic to generate at least one assignable bit according to the plurality of match signals; utilizing a local wordline pre-decoder to generate a local wordline activation signal according to one of at least one bit of the input address and the at least one assignable bit; and in accordance with the input address and the local wordline activation signal, utilizing the one or more spare wordline decoders to activate one spare local wordline from the one or more sets of spare local wordlines for repairing/replacing a defective regular local wordline.

Method and circuitry for handling defective memory cells and wordlines in memory module

Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.

Apparatus for data processing in conjunction with memory array access

Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

DRAM with inter-section, page-data-copy scheme for low power and wide data access

A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Method and apparatus for accumulating and storing respective access counts of word lines in memory module

An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.

Apparatus for enhancing prefetch access in memory module

A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank

A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.

Multi-bank memory device and system

A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

High speed test circuit and method

The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.

Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application

An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Ring oscillator with a two-stage phase blender for generating multi-phase clock signals

A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Growing community of inventors

Hsinchu, Taiwan

Ming-Hung Wang