Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hua Yu

Tze-Liang Lee

Yi-Jing Lee

Tsz-Mei Kwok

Chii-Horng Li

Kun-Mu Li

Jeng-Wei Yu

Tsung-Hsi Yang

Chan-Lon Yang

Pang-Yen Tsai

Li-Wei Chou

Yee-Chia Yeo

Chao-Cheng Chen

Yen-Ru Lee

Lilly Su

Pei-Ren Jeng

Chih-Pin Tsao

Che-Yu Lin

Syun-Ming Jang Jang

Chih-Chiang Chang

Tai-Chun Huang

Yu-Hung Cheng

Shih-Hao Lo

Eric Peng

Yi-Hung Lin

Tetsuji Ueno

Ying Hao Hsieh

Han-Yu Tang

Mong-Song Liang

Ling-Yen Yeh

Hsueh-Chang Sung

Hou-Yu Chen

Chih-Tang Peng

Jr-Hung Li

Li-Li Su

Chia-Wei Chang

Hsien-Hsin Lin

Hao-Ming Lien

Hung-Tai Chang

Weng Chang

Li-Ting Wang

Kuan-Yu Chen

Chien-Chang Su

Yi-Fang Pai

Heng-Wen Ting

Jung-Chi Tai

Cheng-Hsiung Yen

Jung-Jen Chen

Jhi-Cherng Lu

Wei-Siang Yang

Jui-Hsuan Chen

Li-Te S Lin

Chien-Hung Chen

Shih-Chi Lin

Szu-An Wu

Yi-Jing Li

Ying-Chieh Hung

Jet-Rung Chang

Yi-Jung Lee

Ting-Yi Huang

Ying-Hao Hsieh

In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.

Apparatus and method for use with a substrate chamber

In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Method of forming shaped source/drain epitaxial layers of a semiconductor device

A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

Confined source/drain epitaxy regions and method forming same

An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

Semiconductor device having epitaxy source/drain regions

A device includes a fin structure, a gate structure, a first source/drain epitaxial structure and, a second source/drain epitaxial structure. The fin structure over a substrate and includes a bottom portion protruding from the substrate and a top portion over the bottom portion. An interface between the bottom portion and the top portion comprises oxygen and has an oxygen concentration lower than about 1.E+19 atoms/cm. The gate structure covers the fin structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are over the top portion of the fin structure and on opposite sides of the gate structure.

Semiconductor device

A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.

Transistors with stacked semiconductor layers as channels

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Epitaxial growth methods and structures thereof

A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Increasing source/drain dopant concentration to reduced resistance

A semiconductor device includes a substrate, first and second fins over the substrate and extending upwardly in a first direction, an epitaxial material comprising a first portion, a second portion, and a third portion, and a conductive feature in contact with the epitaxial material. The first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions. The third portion has a bottom surface bended upwardly with an apex located between the first and second fins. In a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, the bottom surface has a first straight line and a second straight line intersecting at the apex.

Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same

A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

Semiconductor device and method

A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Dynamic laser-assisted etching

A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Source/drain formation with reduced selective loss defects

In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

Semiconductor device and methods of forming

A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

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Hsinchu, Taiwan

Ming-Hua Yu