United Microelectronics Corp.

Ming-Hua Liu

Sun-Chieh Chien

Chuck Chen

Chen-Chiu Hsue

Eddie Chen

Ming-Tzong Yung

Shu-Ping Lin

A method of removing photoresist at the edge of waters in an integrated circuit the method comprising the following steps. A substrate having at least a MOS component region thereabove is provided. A photoresist layer is formed over the substrate. A pattern is defined on the photoresist layer by exposure and development. The photoresist layer at the edge of the substrate is removed by a chemical reagent and centrifugal effect.

Method of removing photoresist at the edge of wafers

A method of forming a self-aligned contact of a DRAM cell includes providing a substrate having a MOS transistor. The MOS transistor includes a gate and a source/drain region. A first insulating layer, a second insulating layer and a third insulating layer are formed over the surface of the substrate in succession. The third insulating layer is planarized. A contact window mask is formed above the third insulating layer. Using the contact window mask as a cover, the third insulating layer is removed using anisotropic dry etching and isotropic wet etching. Then, a portion of the second insulating layer and a portion of the first insulating layer are removed sequentially to expose the source/drain region so that a self-aligned contact is formed.

Method of forming a self-aligned contact of a DRAM cell

A lightly doped drain (LDD) metal oxide semiconductor field effect transistor (MOSFET). Field oxide is used as a hard mask for a total-overlap polysilicon (TOP) gate which minimizes hot-carrier degradation, so that a soft-mask step is saved. The field oxide is used also as a hard mask for surface counter-doping which reduces gate-induced drain leakage, and in making a punch-through stop which reduces drain-induced barrier low and short channel effect.

Method for fabricating lightly doped drain metal oxide semiconductor

Disclosed is a method of forming self-aligned buried contact implementing self-alignment technology into buried contact process to prevent failure of semiconductor elements due to disconnection of wiring which is caused by misalignment. This is done by forming a sidewall spacer in the recess on the buried contact region. The tolerance of misalignment is greatly increased because a polysilicon layer will contact with the buried contact region if the polysilicon layer could contact the sidewall spacer.

Method of forming self-aligned buried contact

An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

Method for forming a planar field oxide (fox) on substrates for

An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages. The invention also describes a method for forming more gradually sloping steps on the field oxide structure without using a sacrificial layer and a method for planarizing a CVD over a patterned conducting layer using photoresist or spin-on-glass as the sacrificial implant layer.

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Taichung, Taiwan

Ming-Hua Liu