Advanced Semiconductor Engineering, Inc.

Ming-Hsiang Cheng

Tsung-Yueh Tsai

Yi-Shao Lai

Hsiao-Chuan Chang

Ming-Kun Chen

Chung-Hsin Chiang

Kuang-Ting Chi

Chang-Lin Yeh

Jian-Cheng Chen

Jiunn Chen

Tai-Ping Wang

I L Lin

Ken Juang

Chia-Jung Lee

The present disclosure provides a semiconductor package device comprising: (1) a substrate comprising a first area and a second area; (2) a semiconductor device on the first area of the substrate; (3) an antenna pattern on the second area of the substrate; (4) a first electronic component on the antenna pattern; and (5) a first package body encapsulating the first area of the substrate and the semiconductor device and exposing the antenna pattern, the first electronic component and the second area of the substrate. An upper surface of the first package body is non-coplanar with the antenna pattern on the second area of the substrate.

Semiconductor package device and method of manufacturing the same

The present disclosure provides a semiconductor package device comprising a substrate, a semiconductor device, a first electronic component, an antenna pattern and a first package body. The substrate has a first area and a second area. The semiconductor device is disposed on the first area of the substrate. The first electronic component is disposed on the second area of the substrate. The antenna pattern is disposed on the second area of the substrate and electrically connected to the first electronic component. The first package body encapsulates the first area of the substrate and the semiconductor device and exposes the antenna pattern, the first electronic component and the second area of the substrate.

A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.

Semiconductor package having proximity communication signal input terminals and manufacturing methods thereof

A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Semiconductor package

The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

Semiconductor device package having a buffer structure and method of fabricating the same

The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening. Whereby, the non-contact pads of the semiconductor device to be tested face but not in physically contact with the testing pads of the active chip, so as to test the proximity communication between the non-contact pads of the semiconductor device and the testing pads of the active chip.

Apparatus and method for testing non-contact pads of a semiconductor device to be tested

A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.

Semiconductor device package

A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Semiconductor device package having a jumper chip and method of fabricating the same

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.

Semiconductor package and method for making the same

A compact camera module mainly includes an image sensor chip, a module case and a lens module. The image sensor chip has an active surface, a back surface and a plurality of side surfaces, wherein a sensor region is formed in the active surface. A plurality of lateral contact fingers is formed on the side surfaces. The image sensor chip is plugged in a cave of the module case, a plurality of electrically contact components disposed on inside walls of the cave electrically connect the lateral contacting fingers. The lens module is mounted on the module case to seal the image sensor chip. Because the electrically contact components can replace the bonding wires to electrically connect the lateral contacting fingers, the compact camera module can be reworked and tiny.

Compact camera module

An image sensor module including a substrate, an image signal processor, a supporting board, an image sensor chip and a cover is provided. A concavity is located on a surface of the substrate. The image signal processor is disposed in the concavity e, and is electrically connected to the substrate. The supporting board is disposed on the surface of the substrate and covers the concavity. The image sensor chip is disposed on the supporting board and electrically connected to the substrate. The cover is disposed on the substrate, and covers the image sensor chip.

Image sensor module having an image signal processor being physically and electrically unconnected to a supporting board of an image sensor chip

An image sensor package includes a substrate, a lens module and a bottom cover. Herein the substrate has an upper surface and a lower surface, a plurality of passive components is fabricated on the lower surface and a chip is disposed on the upper surface. The lens module is mounted on the substrate and covers the chip. The bottom cover is connected to the lower surface of the substrate to enclose the passive components.

Image sensor package

A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to the first surface of the stiffener ring. A second substrate of a second chip package is secured to the second surface of the stiffener ring. The first substrate is connected to the second substrate through a plurality of solder balls. The heat generated in the first chip package and the second chip package is dissipated by the heat sink. The first chip package and the second chip package are fixed by the stiffener ring to eliminate warpage of the first chip package and the second chip package, thereby assuring the electrical transmission of the product.

Growing community of inventors

Kaohsiung, Taiwan

Ming-Hsiang Cheng