Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsi Yeh

Kuo-Bin Huang

Chun-Neng Lin

Ying-Liang Chuang

Jian-Jou Lian

Chieh-Wei Chen

Ju-Li Huang

Ming-Chi Huang

Po-Nan Yeh

Chi-Ming Yang

Tzu-Ang Chiang

U-Ting Chiu

Chin-Hsiang Lin

Yu-Shih Wang

Po-Yuan Wang

Chun-Hsiang Fan

Yu Shih Wang

Tzu Ang Chiang

Chao-Cheng Chen

Shun Wu Lin

Yu-Chi Pan

Yu-Wen Wang

Syun-Ming Jang Jang

Chun-Sheng Liang

Hsin-Che Chiang

Ying-Hsueh Chang Chien

Tsu-Hui Su

Neng-Jye Yang

Chun-Cheng Chou

Yu-Ming Lin

Clement Hsingjen Wann

Chun Hsiung Tsai

Shahaji B More

Kuo-Feng Yu

Hung-Chin Chung

Kuo Bin Huang

Hsin-Yun Hsu

Chun-Chih Cheng

Liang-Yin Chen

Chia-Cheng Chen

Chia-Ying Lee

Chun-Yi Lee

Hsien-Hsin Lin

Shao-Yen Ku

Li-Min Chen

Chun-Liang Tai

Shian Wei Mao

Hong-Jie Yang

Ssu-Yu Liao

Chia-Ling Chung

Chun-Ming Yang

Ren-Kai Chen

Li-Chen Lee

Chih-Hsin Ko

Chandrashekhar Prakash Savant

Kuo-Sheng Chuang

Tsung-Chieh Tsai

Yi-Fang Pai

Jeng-Shiou Chen

Ming-Chia Tai

Chih-Long Chiang

Kuan-Wei Lin

Shih Min Chang

Wang-Hua Lin

Sung-Hsun Wu

Calvin Chiang

Chia-Chun Kao

Yu-Fang Huang

Yu-Te Su

Huan-Just Lin

Sung-Li Wang

Chih-Tang Peng

Jr-Jung Lin

Yih-Ann Lin

Shuen-Shin Liang

Chia-Hung Chu

Kuo-Ju Chen

Cheng-Wei Chang

Hsu-Kai Chang

Hsin-Hsien Lu

Hao-Ming Lien

Ta-Wei Lin

Yi-Ying Liu

Hui OuYang

Chi-Kang Liu

Bi-Ming Yen

Yu-Fu Lin

Weibo Yu

Bo-Wei Chou

Kao-Feng Lin

Chieh-Yi Shen

Hsin-Yan Lu

Meng-Hsien Li

Chi-Shin Wang

Chih-Nan Lo

Li-min Chen

Ying-Chuen Wang

Shun-Wu Lin

Pei Yun Chung

Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.

Fin shape modification

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

Wet cleaning with tunable metal recess for via plugs

A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.

Method for modifying metal-including material in semiconductor manufacturing process

An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.

Etchant for etching a cobalt-containing member in a semiconductor structure and method of etching a cobalt-containing member in a semiconductor structure

A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Method of breaking through etch stop layer

A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

Fin field-effect transistor and method of forming the same

The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Gate resistance improvement and method thereof

A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.

Semiconductor devices and methods of manufacturing thereof

A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Fin Field-Effect Transistor device and method of forming the same

A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Semiconductor devices and method of forming the same

A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

Fin field-effect transistor device and method of forming the same

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

Semiconductor device and method of manufacture

A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

Fin field-effect transistor device having hybrid work function layer stack

A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

Conductive feature of a semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Ming-Hsi Yeh