Taiwan Semiconductor Manufacturing Comp. Ltd.

Novatek Microelectronics Corp.

Ming-Han Lee

Shau-Lin Shue

Shin-Yi Yang

Yu-Chen Chan

Shu-Wei Li

Hsiang-Huan Lee

Shih-Kang Fu

Tz-Jun Kuo

Meng-Pei Lu

Chin-Lung Chung

Ching-Fu Yeh

Guanyu Luo

Hai-Ching Chen

Hsin-Yen Huang

Hsi-Wen Tien

Chao-Hsien Peng

Hsien-Chang Wu

Chien-Hsin Ho

Chung-Ju Lee

Cheng-Hsiung Tsai

Hsin-Ping Chen

Chung-En Kao

Li-Lin Su

Wen-Cheng Yang

Tung-Ching Tseng

Han-Tang Hung

Chia-Tien Wu

Yung-Hsu Wu

Min Cao

Keith Kuang-Kuo Koai

Chi-Liang Kuo

Wei-Cheng Lin

Chih Wei Lu

Kai-Fang Cheng

Hsiao-Kang Chang

Chieh-Han Wu

Tsung-Jung Tsai

Hwei-Jay Chu

Tzu-Hui Wei

Ding-Teng Shih

An-Dih Yu

Yu-Hao Hsu

Jui-Chang Lin

Pei-Yin Liou

Kuang-Kuo Koai

Cian-Yu Chen

Yun-Chi Chiang

Andy Li

Guan-Shiung Huang

Hsin-Ting Chan

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

Interconnect structure with hybrid barrier layer

A semiconductor device includes a semiconductor substrate, a plurality of intercalated graphene structures and a via. The intercalated graphene structures are disposed over the semiconductor substrate. Each of the intercalated graphene structures includes a plurality of graphene layers each extending substantially parallel to the semiconductor substrate. The via extends into at least a portion of one of the intercalated graphene structures toward the semiconductor substrate, and is in contact with edges of corresponding ones of the graphene layers of the one of the intercalated graphene structures.

Semiconductor device including graphene interconnect and method of making the semiconductor device

A driver integrated circuit for touch sensing and a driving method thereof are provided. The driver integrated circuit includes a touch sensing control circuit. The driver integrated circuit is adapted for driving a touch panel with a touch sensor. The touch sensing control circuit is configured to drive the touch panel to execute a first detection operation. The touch sensing control circuit drives the touch panel to execute a scanning operation after receiving a touch signal. After executing the scanning operation, the touch sensing control circuit drives the touch panel to execute a second detection operation. A sampling frequency of the second detection operation is higher than a sampling frequency of the first detection operation.

Driver integrated circuit for touch sensing and driving method thereof

A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

Interconnect structure including topological material

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

Semiconductor packages and methods for forming the same

A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.

Methods of performing chemical-mechanical polishing process in semiconductor devices

The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Integrated chip with graphene based interconnect

A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction

A semiconductor device includes a first underlying metal line and a second underlying metal line in a first dielectric layer over a substrate. The semiconductor device includes a first metal feature and a second metal feature in a second dielectric layer over the first dielectric layer. The first metal feature is over and connected to the first underlying metal line, and the second metal feature is over and connected to the second underlying metal line. The first metal feature has a first dimension, the second metal feature has a second dimension, the second dimension being greater than the first dimension. The first metal feature includes a first metal having a first mean free path, the second metal feature includes a second metal having a second mean free path, and the second mean free path is greater than the first mean free path.

Interconnect structures having varied materials

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Graphene barrier layer for reduced contact resistance

Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

Interconnect structure without barrier layer on bottom surface of via

A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.

Method for forming semiconductor structure

Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

Hybrid interconnect structure for self aligned via

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Taipei, Taiwan

Ming-Han Lee