United Microelectronics Corp.

Winbond Electronics Corporation

Silicon Integrated Systems Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Faraday Technology Corporation

Ming-Dou Ker

Tien-Hao Tang

Chung-Yu Wu

Kei-Kang Hung

Chau-Neng Wu

Ta-Lee Yu

Chung-Yuan Lee

Joe Ko

Chyh-Yih Chang

Hun-Hsien Chang

Ching-Yun Chu

Wen-Yu Lo

Chien-Chang Huang

Tung-Yang Chen

Yu-Hsuan Li

Yuan-Wen Hsiao

Yuh-Kuang Tseng

Shao-Chi Chen

Tao Cheng

Chien-Ming Lee

Gamma voltage conversion device includes a gamma voltage conversion circuit, an amplifier, and a gamma voltage adjusting circuit. The gamma voltage conversion circuit generates a first gamma voltage conformed to a first gamma curve according to a grey level. The amplifier includes a first input end receiving the first gamma voltage, a second end, and an output end. The amplifier outputs the first or a second gamma voltage conformed to a second gamma curve according to the grey level according to the first and the second ends of the amplifier. The gamma voltage adjusting circuit coupled between the second input end and the output end of the amplifier controls the amplifier to output the first or the second gamma voltage as the gamma driving voltage according to the grey level and a gamma curve selection signal.

Gamma voltage conversion device

The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a bonding wire. The induction structure is coupled with the connection structure and lowers an effective capacitance between the bonding wire and the substrate.

Bonding pad structure disposed in semiconductor device and related method

An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.

ESD protection circuit

A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Low-voltage curvature-compensated bandgap reference

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially depleted or fully-depleted silicon-on-insulator CMOS processes.

Silicon-on-insulator diodes and ESD protection circuits

Voltage dividing resistors (R, R, R, R) are connected in parallel with diode connected bipolar transistors (Q, Q) for splitting the voltage to the inputs of an operational amplifier (). Current is provided to this arrangement by current sources (I, I). When the supply voltage is about 0.85 volts, a temperature insensitive reference voltage of about 200 millivolts is available at the drain of a second transistor (M, M).

Low-voltage bandgap reference

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatible to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P doping region and a first N doping region are in the N-type well and form the anode of the SOI-NSCR. A second P doping region and a second N doping region are in the P-type well and form the cathode of the SOI-NSCR. The first P doping region, the N-type well, the P-type well and the second N doping region form a lateral SCR. A third N doping region is across the N-type well and the P-type well. A gate is in the P-type well, and the third N doping region, the gate and the second N doping region form an NMOS. A dummy gate is in the N-type well for isolating the first P doping region and the third N doping region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created from the N-type well to the P-type well that turns on the SOI-NSCR. When a voltage is applied to the third N doping region, a trigger current is generated that causes the lateral SCR to enter a latch state and so the SOI-NSCR is quickly turned on. Utilizing similar and related designs, the present invention discloses a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), and ESD protection circuitry utilizing the SOI-NSCR and the SOI-PSCR.

Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection

Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process

An ESD protection device is formed on a P-type well, and has at least one NMOS, at least one first P diffusion region for electrically connecting to a P-well biasing circuit, at least one dummy gate between the NMOS and the first P diffusion region, at least one second P diffusion region for electrically connecting to a V power terminal, and at least one shallow trench isolation (STI) structure for isolating the NMOS and the second P diffusion region. A drain of the NMOS, the P-type well, and a source of the NMOS form a parasitic lateral n-p-n bipolar junction transistor (BJT), and the drain and the source of the NMOS are electrically connected to an I/O buffering pad and a V power terminal respectively. When an ESD voltage pulse zaps the I/O buffering pad, the P-well biasing circuit induces a substrate trigger current (I ), causing the parasitic lateral n-p-n BJT to trigger on and quickly discharge a current incurred from the ESD voltage pulse.

MOS structure with improved substrate-triggered effect for on-chip ESD protection

CMOS VLSI chips with pin counts greater than 100 often have multiple power pins to supply sufficient current for circuit operations. In mixed voltage ICs there are separated power pins with different power supplies for specified power operations, and in these ICs the power supplies for the digital and analog circuits are often separated due to noise considerations. In such ICs with separated power pins, the interface circuits between the circuits with different power pins are vulnerable to ESD (electrostatic discharge) stress. Even though there are suitable ESD protection circuits around the input and output pins of the IC, unexpected ESD damage still happens to the interface circuits between the circuits with different power pins, so that a whole-chip ESD protection arrangement using bi-directional SCRs is provided to protect the CMOS ICs against ESD damage. The bi-directional SCRs are placed between the separated power lines of the CMOS IC to provide ESD current discharging paths between the separated power lines. Thus, the vulnerable internal circuits and interface circuits between the different power pins are rendered remote from the ESD damage. The present ESD protection arrangement can be applied to chips having multiple or mixed-voltage power pins.

Whole-chip ESD protection for CMOS ICs using bi-directional SCRs

A capacitor-triggered electrostatic discharge (ESD) protection circuit is disposed between a metal pad and V.sub.ss potential level, wherein the pad may be an input pad, an output pad, or a V.sub.DD power rail. The circuit includes a thick oxide device, a capacitor, and a resistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground V.sub.SS, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is coupled by the resistor to circuit ground V.sub.SS. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout areas. When a positive-to-ground ESD pulse is conducted at the pad, the capacitor will couple the ESD voltage to the well region, forward bias the bulk/source junction, and then turn on the thick oxide device operated in a bipolar mode to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra or built-in PN junction.

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Hsin-Chu, Taiwan

Ming-Dou Ker