Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Chip Engineering Technologies Inc.

Ming-Chih Yew

Po-Yao Lin

Shin-Puu Jeng

Chia-Kuei Hsu

Shu-Shen Yeh

Po-Chen Lai

Chin-Hua Wang

Fu-Jen Li

Po-Hao Tsai

Che-Chia Yang

Kuo-Chuan Liu

Wen-Yi Lin

Li-Ling Liao

Yu-Sheng Lin

Po-Yao Chuang

Tsung-Yen Lee

Shuo-Mao Chen

Ming-Da Cheng

Chen-Shien Chen

Feng-Cheng Hsu

Yu-Tse Su

Yi-Jen Lai

Jiun Yi Wu

Hsiu-Jen Lin

Sey-Ping Sun

Techi Wong

Yang-Che Chen

Hsiu-Mei Yu

Jing Ruei Lu

Chia-Jen Cheng

Shyue-Ter Leu

Kuang-Chun Lee

Cheng-Yi Hong

Chien-Sheng Chen

Chen-Hua Douglas Yu

Hsien-Wei Chen

Der-Chyang Yeh

Chi-Hsi Wu

Li-Hsien Huang

Cheng-Lin Huang

Tsung-Shu Lin

Wei-Ting Lin

Meng-Liang Lin

Yu-Chih Liu

Ming-Shih Yeh

Shih-Ting Hung

Yu-Huan Chen

Hua-Wei Tseng

Bor-Rung Su

Jing-Ye Juang

Shang-Lun Tsai

Chien-Shen Chen

Shyue Ter Leu

Chang-Ann Yuan

Chan-Yen Chou

Kou-Ning Chiang

Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Chip package structure including an underfill material portion comprising a cut region

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Semiconductor package and method of manufacturing the same

Devices and method for forming a chip package structure including a package substrate, a fan-out package attached to the package substrate, a first adhesive layer attached to a top surface of the package substrate, a beveled stiffener structure attached to the package substrate and surrounding the fan-out package, the beveled stiffener structure comprising at least one tapered sidewall, in which a first width of a top portion of the beveled stiffener structure along the at least one tapered sidewall is greater than a second width of a bottom portion of the beveled stiffener structure along the at least one tapered sidewall, and in which the bottom portion is in contact with a top surface of the first adhesive layer.

Stiffener structure with beveled sidewall for footprint reduction and methods for forming the same

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Integrated circuit package and method of forming same

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Package structure

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Buffer block structures for C4 bonding and methods of using the same

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Semiconductor device and method of manufacture

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure comprising fan-out bonding pads, and a first underfill material portion, a packaging substrate comprising chip-side bonding pads, solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads, a second underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the second underfill material portion and having a Young's modulus that is lower than a Young's modulus of the second underfill material portion.

Underfill cushion films for packaging substrates and methods of forming the same

A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

Semiconductor chip package having underfill material surrounding a fan-out package and contacting a stress buffer structure sidewall

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a surface of the substrate. The ring structure is located over the surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the surface of the substrate and a top surface opposite the bottom surface. The ring structure includes recesses recessed from and located on the top surface, wherein the recesses are arranged corresponding to the corners of the substrate. The adhesive layer is interposed between the bottom surface of the ring structure and the surface of the substrate.

Semiconductor device package having warpage control and method of forming the same

A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.

Method for forming semiconductor package structure

A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.

Dual-underfill encapsulation for packaging and methods of forming the same

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Organic interposer including intra-die structural reinforcement structures and methods of forming the same

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Hsinchu, Taiwan

Ming-Chih Yew