Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Chip Engineering Technologies Inc.

Ming-Chih Yew

Po-Yao Lin

Shin-Puu Jeng

Chia-Kuei Hsu

Shu-Shen Yeh

Po-Chen Lai

Chin-Hua Wang

Fu-Jen Li

Po-Hao Tsai

Che-Chia Yang

Kuo-Chuan Liu

Wen-Yi Lin

Po-Yao Chuang

Li-Ling Liao

Yu-Sheng Lin

Tsung-Yen Lee

Ming-Da Cheng

Chen-Shien Chen

Shuo-Mao Chen

Yu-Tse Su

Feng-Cheng Hsu

Yi-Jen Lai

Jiun Yi Wu

Hsiu-Jen Lin

Sey-Ping Sun

Techi Wong

Yang-Che Chen

Hsiu-Mei Yu

Jing Ruei Lu

Chia-Jen Cheng

Shyue-Ter Leu

Kuang-Chun Lee

Cheng-Yi Hong

Chien-Sheng Chen

Chen-Hua Douglas Yu

Hsien-Wei Chen

Der-Chyang Yeh

Chi-Hsi Wu

Cheng-Lin Huang

Li-Hsien Huang

Tsung-Shu Lin

Wei-Ting Lin

Yu-Chih Liu

Meng-Liang Lin

Ming-Shih Yeh

Shih-Ting Hung

Yu-Huan Chen

Hua-Wei Tseng

Bor-Rung Su

Jing-Ye Juang

Shang-Lun Tsai

Chien-Shen Chen

Shyue Ter Leu

Chang-Ann Yuan

Chan-Yen Chou

Kou-Ning Chiang

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Semiconductor device and method of manufacture

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure comprising fan-out bonding pads, and a first underfill material portion, a packaging substrate comprising chip-side bonding pads, solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads, a second underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the second underfill material portion and having a Young's modulus that is lower than a Young's modulus of the second underfill material portion.

Underfill cushion films for packaging substrates and methods of forming the same

A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

Semiconductor chip package having underfill material surrounding a fan-out package and contacting a stress buffer structure sidewall

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a surface of the substrate. The ring structure is located over the surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the surface of the substrate and a top surface opposite the bottom surface. The ring structure includes recesses recessed from and located on the top surface, wherein the recesses are arranged corresponding to the corners of the substrate. The adhesive layer is interposed between the bottom surface of the ring structure and the surface of the substrate.

Semiconductor device package having warpage control and method of forming the same

A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.

Method for forming semiconductor package structure

A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.

Dual-underfill encapsulation for packaging and methods of forming the same

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Organic interposer including intra-die structural reinforcement structures and methods of forming the same

A semiconductor package includes a die, a first conductive pattern, a second conductive pattern and first and second under-ball metallurgy (UBM) patterns. The first conductive pattern and the second conductive pattern are disposed below and electrically connected to the die, wherein the first conductive pattern has an ellipse-like shape, and the second conductive pattern has a circular shape. The first and second under-ball metallurgy (UBM) patterns correspond to the first and second conductive patterns, the first conductive pattern has a first length, the second conductive pattern has a second length, the first and second UBM patterns have a third length, wherein the first length is larger than the third length and the second length is smaller than the third length.

Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape

A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of package substrate surrounding the semiconductor devices; a cover disposed over the package ring and the semiconductor devices; a cover adhesive bonding the cover to the package ring; and a stress-reduction structure including first channels formed in an upper surface of the package ring and second channels formed in a lower surface of a portion of the cover that overlaps with the first channels.

Semiconductor package including stress-reduction structures and methods of forming the same

A package assembly includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and attached to the package substrate. The package lid includes an outer lid including an outer lid material and including an outer lid plate portion. The package lid further includes an inner lid including an inner lid material different than the outer lid material and including an inner lid plate portion attached to a bottom surface of the outer lid plate portion.

Package assembly lid and methods for forming the same

Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.

Semiconductor die with tapered sidewall in package

A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

Semiconductor device package having dummy dies

A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar. The semiconductor device is disposed over the first surface of the redistribution structure, wherein the semiconductor device comprises a third conductive pillar and a fourth conductive pillar, the third conductive pillar is bonded to first conductive pillar through a first joint structure, and the fourth conductive pillar is bonded to second conductive pillar through a second joint structure.

Semiconductor package and method of forming the same

Growing community of inventors

Hsinchu, Taiwan

Ming-Chih Yew