Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Chih Chung

Jyh-Feng Lin

Shun-Hsiang Chen

Kuen-Joung Chuang

Hon-Shung Lui

Jin-Yuan Lee

Jenn-Ming Huang

An improved method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched through the insulating layer to the underlying semiconductor device structures wherein a tunnel opens in the insulating layer between contact openings. The semiconductor substrate is covered with a first barrier metal layer. The semiconductor substrate is coated with a spin-on-glass layer wherein the contact openings and the tunnel are filled with the spin-on-glass. The spin-on-glass is anisotropically etched away whereby the spin-on-glass remains only within the tunnel. The semiconductor substrate is covered with a second barrier metal layer. The contact openings are filled with tungsten which is etched back to form tungsten plugs within the contact openings wherein the filled tunnel provides tunnel-free tungsten plugs in the fabrication of the integrated circuit device.

Tungsten tunnel-free process

The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has 'oxide steps' (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

Stepped edge structure of an EEPROM tunneling window

Method of making stepped edge structure of an EEPROM tunneling window

An SRAM transistor cell on a doped semiconductor substrate comprises a first pass transistor and a second pass transistor, a first driver transistor and a second driver transistor and a saturated mode transistor. The device includes a first and second load resistor, first second and third nodes, a bit lines and interconnection lines. The first driver transistor drain region is connects to the first node. The control gate electrode cross connects via the first interconnection line to the second node. The second driver transistor drain region connects to the third node and the control gate electrode cross connects via the second interconnection line to the first node. The control gate electrodes of the pass transistors connect to a single input line. The drain region of the first pass transistor connects to the first node. The drain region of the second pass transistor connects to the second node. The source region of the first pass transistor connect to the bit line bar. The source region of the second pass transistor is connects to the bit line. The drain region and control gate electrode of the saturated mode transistor connect to the second node and the source region of the saturated mode transistor connects to the third node.

Trench free SRAM cell structure

A method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched through the insulating layer to the underlying semiconductor device structures wherein a tunnel opens in the insulating layer between contact openings. The semiconductor substrate is covered with a first barrier metal layer. The semiconductor substrate is coated with a spin-on-glass layer wherein the contact openings and the tunnel are filled with the spin-on-glass. The spin-on-glass is anisotropically etched away whereby the spin-on-glass remains only within the tunnel. The semiconductor substrate is covered with a second barrier metal layer. The contact openings are filled with tungsten which is etched back to form tungsten plugs within the contact openings wherein the filled tunnel provides tunnel-free tungsten plugs in the fabrication of the integrated circuit device.

Growing community of inventors

Hsin-Chu, Taiwan

Ming-Chih Chung