Advanced Semiconductor Engineering, Inc.

Ase Electronics Inc.

Ming-Chiang Lee

Yuan-Chang Su

Chien-Hao Wang

You-Lung Yen

Bernd Karl Appelt

Shih-Fu Huang

Chih-Cheng Lee

Ho-Ming Tong

Teck-Chong Lee

Jau-Shoung Chen

Tien-Szu Chen

Jen-Chieh Kao

Chun-Che Lee

Kuo-Hua Chen

Cheng-Nan Lin

Shin-Hua Chao

Tai-Yuan Huang

Tsung-Hsun Lee

Chao-Yuan Liu

Chen-Chuan Fan

Yung-Cheng Huang

Kuang-Hsiung Chen

Hsu-Nan Fang

Yung-I Yeh

Yung I Yeh

Chun-Jun Zhuang

Chia-Cheng Chen

Min-Yao Chen

Chia-Hsiung Hsieh

Kuo Hsien Liao

Mao-Chang Chuang

A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

Semiconductor device package

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Semiconductor substrate and method for manufacturing the same

A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.

Semiconductor device package and method of manufacturing the same

Semiconductor substrate mitigating bridging

A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Substrate structure and package structure using the same

The semiconductor package includes a substrate, a plurality of components, an interposer, an electrical interconnect and a first package body. The substrate has a first surface and a second surface opposite to the first surface. A first component is mounted on the first surface of the substrate, and a second component is mounted on the second surface of the substrate. The interposer has a first surface. The electrical interconnect connects the first surface of the interposer to the second surface of the substrate. The first package body is disposed on the second surface of the substrate and encapsulates the second component, the electrical interconnect and at least a portion of the interposer.

Semiconductor package structure and semiconductor process

A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

Method of fabricating a multi-trace via substrate

A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

Chip package

The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

Coreless substrate and method for making the same

An embedded circuit substrate comprising: a core structure having a first surface and a second surface opposite to each other; a first patterned conductive layer disposed on the first surface and embedded in the core structure; a second patterned conductive layer disposed on the second surface and embedded in the core structure; and a plurality of conductive blocks disposed in the core structure for conducting the first patterned conductive layer and the second patterned conductive layer is provided. Furthermore, a manufacturing method of an embedded circuit substrate is also provided.

Manufacturing method of embedded circuit substrate

In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof

An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

Embedded component substrate and manufacturing methods thereof

A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

Semiconductor package with substrate having single metal layer and manufacturing methods thereof

The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

Growing community of inventors

Kaohsiung, Taiwan

Ming-Chiang Lee