Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Che Ho

Hung-Jui Kuo

Chung-Shi Liu

Yi-Wen Wu

Tzung-Hui Lee

Chen-Hua Douglas Yu

Kai-Chiang Wu

Chien Ling Hwang

Zheng-Yi Lim

Shih-Hao Tseng

Chih-Wei Lin

Tzong-Hann Yang

Hao-Yi Tsai

Ming-Da Cheng

Mirng-Ji Lii

Yu-Feng Chen

Tuan-Yu Hung

Chi-Ming Tsai

Hsien-Liang Meng

Han-Ping Pu

Wen-Hsiung Lu

Yen-Liang Lin

Chun-Hung Lin

Ming Hung Tseng

Tzu-Sung Huang

Ching-Wen Chen

Chia-Tung Chang

Chun-Lei Hsu

Alexander Kalnitsky

Wei-Hung Lin

Hsiu-Jen Lin

Shih-Wei Liang

Chin-Yu Ku

Ching-Feng Yang

Chia-Hung Liu

Ching-Hui Chen

Chien Rhone Wang

Chih-Wei Lai

Wei-Chung Chang

Tzu-Yun Huang

Tzu Yun Huang

Chewn-Pu Jou

Yu-Hsiang Hu

Hung-Yi Kuo

Tsung-Yuan Yu

Cheng-Chieh Hsieh

Chih-Hang Tung

Kuo-Chio Liu

Yu-min Liang

Cheng-Chung Lin

Chia-Wei Tu

Chung-Ming Weng

Jean Wang

Meng-Wei Chou

De-Yuan Lu

Hua-Kuei Lin

Cheng-Tse Tang

Chiang-Hao Lee

Wei-Yu Chen

Ching-Hua Hsieh

Jui-Pin Hung

Hui-Jung Tsai

Chun-Lin Lu

Hsin-Yu Pan

Yi-Li Hsiao

Chien-Ling Hwang

Yu-Peng Tsai

Hsuan-Ting Kuo

Chih-Chiang Tsao

Tzu-Chun Tang

Zi-Jheng Liu

Chia-Shen Cheng

Chia-Lun Chang

Ming-Tan Lee

Yu-Ming Lee

Cheng-Shiuan Wong

Lawrence Chiang Sheu

Yen-Fu Su

Jimmy Liang

Cheng Hsun Chan

Kuo Cheng Lin

Kio-Chio Liu

A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.

Semiconductor packages and method of manufacturing the same

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.

Integrated circuit package and method

A manufacturing method of a semiconductor package includes the following steps. An integrated circuit structure is provided, wherein the integrated circuit structure includes an integrated circuit and a metallization layer covering a back surface of the integrated circuit. An encapsulation material is provided to laterally encapsulate the integrated circuit structure. A redistribution structure is provided over the integrated circuit structure and the encapsulation material, wherein the redistribution structure includes a thermal metal layer furthermost from the integrated circuit structure, wherein the thermal metal layer is thermally coupled to the metallization layer. A solder layer is provided over the thermal metal layer, wherein the solder layer is thermally coupled to the thermal metal layer.

Manufacturing method of semiconductor package

A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

Semiconductor package having composite seed-barrier layer and method of forming the same

Provided is a package structure including a die; an electrically connecting structure having a die attach region and a peripheral region surrounding the die attach region, wherein the die is disposed on the electrically connecting structure within the die attach region; an insulating protrusion disposed in the peripheral region and extending in a thickness direction of the die; a conductive structure disposed on the electrically connecting structure and encapsulating the insulating protrusion, wherein the conductive structure is electrically coupled to the electrically connecting structure and the die; and a dielectric structure disposed on the electrically connecting structure and encapsulating the die and the conductive structure.

Package structure and method of fabricating the same

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Semiconductor package

A semiconductor structure and a method of forming the same are disclosed. A method of forming a semiconductor structure includes the following operations. An insulating layer is formed over a substrate. A metal feature is formed in the insulating layer. An argon-containing plasma treatment is performed to the insulating layer and the metal feature.

Semiconductor structure and method of forming the same

A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.

A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Semiconductor package and manufacturing method thereof

Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

Integrated fan-out (InFO) package structure

In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.

Semiconductor package and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Semiconductor device and method

Growing community of inventors

Tainan, Taiwan

Ming-Che Ho