Advanced Semiconductor Engineering, Inc.

Min-Lung Huang

Ching-Huei Su

Chao-Fu Weng

Jen-Kuang Fang

Ho-Ming Tong

Chun-Chi Lee

Jau-Shoung Chen

Yung-Chi Lee

Yu-Chen Chou

Tsung-Hua Wu

Su Tao

Wei-Chung Wang

Kuo-Chung Yee

Po-Jen Cheng

Chian-Chi Lin

Chi-Long Tsai

Jian-Wen Lo

Yi-Chuan Ding

Shih-Chang Lee

Yung-I Yeh

Yung-Jen Chen

Chuehan Hsieh

En-Chieh Wu

Hung-Jen Yang

Chia-Ming Chuang

Yang Hong-Zen

In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

Semiconductor device having conductive via and manufacturing process for same

Semiconductor device having conductive via and manufacturing process

Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.

Semiconductor device packages, redistribution structures, and manufacturing methods thereof

A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.

Three-dimensional package and method of making the same

A semiconductor device package includes a semiconductor device, a sealant, a first dielectric layer, an electrically conductive layer, and a second dielectric layer. The semiconductor device includes a contact pad, an active surface, and side surfaces, where the contact pad is disposed adjacent to the active surface. The semiconductor device is formed with a first alignment mark that is disposed adjacent to the active surface. The sealant envelopes the side surfaces of the semiconductor device and exposes the contact pad. The first dielectric layer is disposed adjacent to the sealant and the active surface, and defines a first aperture that exposes the contact pad. The electrically conductive layer is disposed adjacent to the first dielectric layer and is electrically connected to the contact pad through the first aperture. The second dielectric layer is disposed adjacent to the electrically conductive layer.

Semiconductor device package with an alignment mark

A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are 'inserted' into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.

A method for forming a redistribution layer in a wafer structure, including (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive structures; (b) forming a second passivation layer over the first passivation layer; (c) selectively removing part of the second passivation layer to form a plurality of grooves corresponding to a predetermined circuit; (d) forming a redistribution layer in the grooves; and (e) forming a third passivation layer over the second passivation layer and the redistribution layer. As a result, the redistribution layer is 'embedded' in the second passivation layer so as to avoid the delamination of the redistribution layer.

Method for forming a redistribution layer in a wafer structure

The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Method of forming bumps

A screen printing method of conductive material is applied to a wafer with a conductive surface thereon. A dielectric layer on the wafer exposes the conductive surface to a first opening. A mask formed on the dielectric layer has a plurality of second openings corresponding to the first opening. The conductive surface is exposed by the second openings. The conductive surface is covered with a conductive material that flows into the first opening through the second openings. Then the mask is removed. With the arrangement and dimension control of the second openings, the conductive material easily flows into the first opening and is not over-scraped.

Screen printing method of forming conductive bumps

The present invention provides a wafer structure having a plurality of bonding pad, an adhesion layer, a barrier layer, a wetting layer, a plurality of bump, a first passivation layer and a second passivation layer. The bonding pads are disposed on the active surface of the wafer and exposed by the first passivation layer. The second passivation layer is disposed on the first passivation layer and exposing the bonding pads. An adhesion layer is disposed on the bonding pad and covers a portion of the first passivation layer. The second passivation layer covers the first passivation layer and a portion of the adhesion layer. The barrier layer and the wetting layer are sequentially disposed on the adhesion layer and the bumps are disposed on the wetting layer.

Bump electrodes having multiple under ball metallurgy (UBM) layers

A method of forming a plurality of bumps over a wafer mainly comprises providing the wafer having a plurality of bonding pads formed thereon, forming an under bump metallurgy (UBM) layer over the bonding pads wherein the UBM layer includes an adhesive layer, for example a titanium (Ti) layer or an aluminum (Al) layer, and at least one electrically conductive layer formed on the adhesive layer, removing the portions of the electrically conductive layer located outside the bonding pads, forming a plurality of bumps over the residual portions of the electrically conductive layer disposed above the bonding pads, etching the adhesive layer located outside the bumps, and then reflowing the bumps.

Bumping process

A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

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Kaohsiung, Taiwan

Min-Lung Huang