Taiwan Semiconductor Manufacturing Comp. Ltd.

Min Jiao

Da-Wen Lin

Ming-Yuan Wu

Ka-Hing Fung

Hung-Ju Chou

Ji-Yin Tsai

Yi-Ting Fu

Hsu-Chieh Cheng

Wei-Yuan Jheng

A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

Method of fabricating a gate cut feature for multi-gate semiconductor devices

The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness ton the substrate at a second temperature T; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature Tless than T, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.

Method and multi-channel devices with anti-punch-through features

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature Tis lower than the temperature T

Semiconductor devices with low leakage current and methods of fabricating the same

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Hsinchu, Taiwan

Min Jiao