Vanguard International Semiconductor Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Worldwide Semiconductor Mfg. Corp.

Worldwide Semiconductor Corporation

Min-hwa Chi

Yeur-Luen Tu

Chia-Shiung Tsai

Chih-Yuan Lu

Dahcheng Lin

Chih-Hsing Yu

Chih Ming Chen

George Meng-Jaw Cherng

Chih-Ming Chen

Chine-Gie Lou

Yuan-Hung Liu

Chih-Yang Pai

Hong-Hsiang Tsai

Ming-Zen Lin

Dah Lin

Min-Chie Jung

A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ 'GIDL switches' by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the Vand V. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.

Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents

A method for fabricating an MIM capacitor on a substrate. A region of the substrate is dedicated for use as an electrode area of the MIM capacitor. The electrode area of the MIM capacitor may be increased by utilizing at least one spacer formed on an associated planar metal surface, wherein the planar metal surface is formed upon the substrate. An increase in a gain factor of the electrode area is thus dependent upon an associated spacer height and particular number of islands or vias. A roughened surface is thus created for use as a roughened electrode for subsequent capacitor processes. Fabricating spacers made of conducting or non-conducting materials on the associated planar metal surface can create such an electrode. The MIM capacitor formed thereof can be utilized in mixed-signal and RF applications and is fully compatible with COMS logic fabrication processes.

Low temperature MIM capacitor for mixed-signal/RF applications

A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.

Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer

A charge pump formed in a silicon-on-insulator (SOI) substrate is disclosed. The charge pump comprises a SOI layer formed on a substrate. Formed in the silicon of the SOI is a first p-body and a second p-body. Also formed in the silicon is a n&plus; region that extends down to the insulator so that the n&plus; region separates the first p-body and second p-body. Finally, a gate structure is formed atop of a portion of the first p-body and a portion of the n&plus; region. The gate structure is separated from the 1 p-body and n&plus; region by gate oxide, and it serves as charge pump capacitor. Both the diode turn-on (when gate is pulsing high and forward biasing the p-body to n&plus; junction), and GIDL current (when the gate is pulsing low, and generates GIDL hole currents from n&plus; surface to p-body) will result in a &ldquo;short&rdquo; of the p-body and n&plus; region; this ensures the proper operation of charge pump.

Charge pump device formed on silicon-on-insulator and operation method

Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450&deg; C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity. After the capacitor cavity is formed by either method, the sidewall of the deep cavity is coated sequentially with a conformal conducting film as the bottom electrode and a high-k dielectric, and then filled with a conducting material to form the top electrode.

Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications

Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.

Methods for forming memory cell structures

A structure with bit lines and capacitors for a semi-conductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise

A method of reading a 2-bit p-channel memory cell having a p&plus; drain, a p&plus; source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands. The p&plus; drain and the p&plus; source is formed in an n-well. The method comprises: applying a positive voltage to the control gate to generate a gate induced drain leakage (GIDL) current; and measuring a drain GIDL current at the drain and a source GIDL current at the source simultaneously to determine the 2-bit data stored in the memory cell.

Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate

A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n&plus; and p&plus; junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n&plus; or P&plus; &ldquo;GIDL switches&rdquo; by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the V,and V,. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for highperformance, low-voltage, and low-power VLSI circuits on SOI wafers.

Transistor and logic circuit of thin silicon-on-insulator wafers based on gate induced drain leakage currents

A two-dimensional array of single polysilicon DRAM cells is disclosed. The array comprises a plurality of DRAM cells arranged in a two-dimensional matrix, wherein each of the DRAM cells comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well; and a n,region within the p-well and adjacent to a sidewall of the gate structure. The array is connected together by a plurality of column bitlines, each of the column bitlines connected to the n,regions of all of the DRAM cells that are in a common column. Further, a plurality of row wordlines are provided, each of the row wordlines connected to the gate structures of all of the DRAM cells that are in a common row.

Single polysilicon DRAM cell and array with current gain

A current source formed in a p-type substrate is disclose. First, a deep n-well is formed within the p-type substrate and a buried n&plus; layer is formed within the deep n-well. Next, a p-well is formed within the deep n-well and atop the buried n&plus; layer. The p-well and deep n-well are then surrounded by an isolation structure that extends from the surface of the substrate to below the level of the p-well. A n&plus; reference structure is formed within the p-well and a gate is formed above the p-well, the gate separated from the substrate by a thin oxide layer, the gate extending over at least a portion of the n&plus; reference structure. Finally, a n&plus; output structure is formed within the p-well. An input reference current is provided to the n&plus; reference structure and an output current is provided by the n&plus; output structure.

Current source using merged vertical bipolar transistor based on gate induced gate leakage current

A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.

Method for reading 2-bit ETOX cells using gate induced drain leakage current

A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700&deg; C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.

Method to fabricate DRAM capacitor

A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Growing community of inventors

Hsinchu, Taiwan

Min-hwa Chi