Taiwan Semiconductor Manufacturing Comp. Ltd.

Min-Hsiu Hung

Cheng-Wei Chang

Yi-Hsiang Chao

Chih-Wei Chang

Huang-Yi Huang

Hung-Yi Huang

Yu-Ting Lin

Ya-Yi Cheng

Ming-Hsing Tsai

Ken-Yu Chang

Chih-wei Chang

Chun-I Tsai

Chia-Han Lai

Pin-Wen Chen

Chun-Hsien Huang

Ching-Hwanq Su

Wei-Jung Lin

Yi-Ying Liu

Chien Chang

Mei-Hui Fu

Chun-Wen Nieh

Chun Chieh Wang

Kan-Ju Lin

Kao-Feng Lin

Kai-Chieh Yang

Kuan-Yu Yeh

Yu-Chen Ko

Yu-Ting Wen

Yee-Chia Yeo

Sung-Li Wang

Cheng-Tung Lin

Chi-On Chui

Jyh-Cherng Sheu

Chang-Ting Chung

Pei-Wen Wu

Yida Li

Chi On Chui

Yen-Ming Chen

Li-Zhen Yu

Dian-Hau Chen

Chun-Chieh Wang

Chien-Hao Chen

Hsiang-Ku Shen

Chih-Tang Peng

Jr-Hung Li

Li-Wei Chu

Chen-Yuan Kao

De-Wei Yu

Ying-Liang Chuang

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Peng-Fu Hsu

Yen-Chun Huang

Cheng-Po Chau

Chia-Lin Chuang

Jin-Mu Yin

Yu-Hsiang Liao

Chun-Cheng Chou

Ya-Huei Li

Chi-Hung Chuang

Peng-Hao Hsu

Yu-Syuan Cai

Shih-Wei Yeh

A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Method of forming conductive feature including cleaning step

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Fin field-effect transistor device and method of forming the same

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.

Methods of forming semiconductor device structures

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Contact features of semiconductor device and method of forming same

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Method of fabricating contact structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Conductive feature formation and structure

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Selective formation of titanium silicide and titanium nitride by hydrogen gas control

In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Interconnect structures including a fin structure and a metal cap

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

Conductive feature structure including a blocking region

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Semiconductor device structure with salicide layer and method for forming the same

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Tainan, Taiwan

Min-Hsiu Hung