International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Min Dai

Michael Patrick Chudzik

Jinping Liu

Shahab Siddiqui

Joseph Francis Shepard, Jr

Takashi Ando

Siddarth A Krishnan

Yanxiang Liu

Maryjane Brodsky

Xiaodong Yang

Martin Michael Frank

Barry P Linder

Dominic Joseph Schepis

Shreesh Narasimha

Unoh Kwon

Rishikesh Krishnan

Yanfeng Wang

Claude Ortolland

Balaji Kannan

Murshed Mahmud Chowdhury

Vara Govindeswara Reddy Vakada

David F Hilscher

Xiang Hu

Paul Andrew Ronsheim

Keith K H Wong

Srinivasan Rangarajan

Bing Sun

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Hydroxyl group termination for nucleation of a dielectric metallic oxide

Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

Field effect transistors having multiple effective work functions

A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

Fabrication of higher-K dielectrics

Fabrication of higher-k dielectrics

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Semiconductor device including graded gate stack, related method and design structure

A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure

Systems and methods for performing X-ray Photoelectron Spectroscopy (XPS) measurements in a semiconductor environment are disclosed. A reference element peak is selected and tracked as part of the measurement process. Peak shift of the reference element peak, in electron volts (eV) is tracked and applied to other portions of acquired spectrum to compensate for the shift, which results from surface charge fluctuation.

Dynamic peak tracking in X-ray photoelectron spectroscopy measurement tool

Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Concurrently forming nFET and pFET gate dielectric layers

A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

Composite high-k gate dielectric stack for reducing gate leakage

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer

A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

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Mahwah, NJ, United States of America

Min Dai