Entegris, Inc.

Winbond Electronics Corporation

Min-Chieh Yang

Hsing-Chen Wu

Emanuel Israel Cooper

Steven M Bilodeau

Ming-Chung Chiang

SeongJin Hong

Chung-Ming Chu

Sheng-Hung Tu

Bor-Ru Sheu

Li-Min Chen

Wen-Chung Liu

Jong-Bor Wang

Sean Kim

Pai-Hsuan Sun

Wen Hua Tai

Wei-Ling Lan

Ming-Chi Liao

Wen-Haw Dai

Bor-Bu Sheu

The present invention relates to compositions and methods for selectively etching silicon nitride in the presence of silicon oxide, polysilicon and/or metal silicides at a high etch rate and with high selectivity. Additives are described that can be used at various dissolved silica loading windows to provide and maintain the high selective etch rate and selectivity.

Selective etchant compositions and methods

Provided are compositions and methods useful in etching, i.e., removing amorphous carbon hard masks which have been doped with elements such as boron, chlorine, or nitrogen. The compositions utilize concentrated sulfuric acid, water, and at least one oxidizing agent. In the operation of the method, the composition selectively removes the doped hard mask layer, even in the presence of layers such as silicon dioxide, silicon nitride, tantalum nitride, and polysilicon, with good selectivity.

Method for removing hard masks

Compositions useful for the selective removal of silicon nitride materials relative to polysilicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon are provided. The compositions of the invention are particularly useful in the etching of 3D NAND structures.

Silicon nitride etching composition and method

Described are compositions and methods useful for wet-etching a microelectronic device substrate that includes silicon nitride; the compositions including phosphoric acid, hexafluorosilicic acid, and an amino alkoxy silane, and optionally one or more additional optional ingredients; a wet etching method of a substrate that includes silicon nitride and silicon oxide, that uses a composition as described, can achieve useful or improved silicon nitride etch rate, useful or improved silicon nitride selectivity, a combination of these, and optionally a reduction in particles present at a substrate surface after etching.

Compositions and methods for etching silicon nitride-containing substrates

Compositions useful for the passivation of germanium-containing materials on a microelectronic device having same thereon.

Passivation of germanium surfaces

Liquid compositions useful for the cleaning of residue and contaminants from a III-V microelectronic device material, such as InGaAs, without substantially removing the III-V material. The liquid compositions are improvements of the SC1 and SC2 formulations.

Compositions for cleaning III-V semiconductor materials and methods of using same

The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

Memory-storage node and the method of fabricating the same

A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

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Hsinchu, Taiwan

Min-Chieh Yang