Mitsubishi Denki Kabushiki Kaisha

Mikihiro Kimura

Mitsunori Tsujino

Masahiro Sekine

An A1 pad (11) is provided on a field oxide film isolation (5). The A1 pad (11) is electrically connected to a gate electrode (7) with an A1 wiring pattern (10) and the like. In measurement, a probe (3) comes into contact with the A1 pad (11) to apply a voltage thereto. The probe (3) does not come into direct contact with the gate electrode (7), and therefore no stress is applied to a region below a gate insulation film (6) in which a depletion layer is to be created. With this structure, more accurate result is obtained in a test of estimating defects at an isolation edge using a C-t measurement method.

Semiconductor test structure for estimating defects at isolation edge

A semiconductor device is obtained in which initial breakdown voltage of an insulating film is improved. On a silicon substrate, an insulating film is provided which is not more than 100 .ANG. in thickness. An electrode is provided on the silicon substrate, with the insulating film positioned therebetween. Oxygen concentration in the substrate is set to be not more than 1.times.10.sup.18 atoms/cm.sup.3 by old ASTM value.

Semiconductor device

It is an object to obtain evaluation results with a dielectric film evaluating test structure which are close to those with an actual device. Gate electrodes (6A) are provided in a dielectric film evaluating test structure. In the gate electrodes 6A, openings (20) are formed on a gate insulator film (5) by etching, or the like.

Test structure for dielectric film evaluation

An apparatus for measuring an electrical characteristic of a semiconductor device, particularly for determining the dependence of leakage current of the semiconductor device with time or after a stress is applied to the semiconductor device. An accumulator counts pulses of an internal clock thereby separately determining the time during which a stress is applied and the time during which a measurement is made. These two times are recorded with the measured characteristic, such as leakage current. The measured characteristic is plotted on the basis of the duration of the applied stress and duration of the measurement and displayed.

Apparatus including a measurement time counting device for measuring an

A superlattice semiconductor device comprises superlattice layers (4a, 4a', 5a) stacked on the whole surface of a trench (20) formed in a semiconductor substrate or on the whole surface of a projection (30) extending from a surface of the semiconductor substrate.

Superlattice semiconductor device

An accurate dielectric breakdown prediction method and a prediction method in which accurate time dependent dielectric breakdown (TDDB) characteristics can be obtained on the basis of dielectric breakdown prediction by a step stress method are provided. In this method, dielectric breakdown is predicted on the basis of a plurality of reference currents in accordance with an applied voltage, or a reference current I.sub.cr is varied as the function of the applied voltage. In the step stress TDDB prediction, a Chen-Holland-Hu model or improved Chen-Holland-Hu model is employed. Since TDDB characteristics can be obtained from only dielectric breakdown prediction, this method is advantageous for early reliability prediction.

Dielecrtric breakdown prediction apparatus and method, and dielectric

Dielectric breakdown prediction and dielectric breakdown life-time

A flat band voltage of a MIS structure is determined by measuring high-frequency C-V characteristics thereof, and a surface potential is calculated by the definite integral processing as a function of the flat band voltage. Ideal C-V characteristics of the MIS structure are determined from the surface potential. By comparing measured low-frequency or quasi-static C-V characteristics with the ideal C-V characteristics, the distribution of an interface state density is determined. Thus, the flat band voltage of an ideal C-V curve coincides with the flat band voltage of a low-frequency or quasi-static C-V curve, so that the interface state density distribution in the MIS structure can be accurately measured.

Method of measuring interface state density distribution in MIS structure

A solid-state image sensing device has an overflow drain structure for purging superfluous charges. The overflow drain structure includes a gate electrode (34), channel regions (35), and a drain region (32) formed inside each groove (26) formed on a main surface of a semiconductor substrate (6). Optoelectro transducers (4) are formed on main surface regions of the semiconductor substrate continuous with each groove. The drain region is formed on side walls and a bottom wall of each groove by oblique ion implantation. The overflow drain structure formed inside the groove occupies a reduced area on the main surface of the semiconductor substrate and increases its opening ratio.

Method of manufacturing a solid-state image sensing device having an

A solid state image sensing device comprises photoelectric converting portions (8) and charge coupled portions. A plurality of parallel trenches (2) are formed on a main surface of a semiconductor substrate (1). Photoelectric converting portions are on the surfaces of the semiconductor substrate on both sides of each of the trenches. Charge transfer portions corresponding to the photoelectric converting portions are independently formed on the side surfaces of the trenches. Insulating and isolating regions (15, 29, 30) are formed on the bottom portions of the trenches. By providing two independent charge transfer portions in one trench, the area occupied by the charge transfer portions can be reduced.

Method for manufacturing solid state image sensing device formed of

A solid-state image sensing device has an overflow drain structure for purging superfluous charges. The overflow drain structure includes a gate electrode (34), channel regions (35), and a drain region (32) formed inside each groove (26) formed on a main surface of a semiconductor substrate (6). Optoelectro transducer (4) are formed on main surface regions of the semiconductor substrate continuous with each groove. The drain region is formed on side walls and a bottom wall of each groove by oblique ion implantation. The overflow drain structure formed inside the groove occupies a reduced area on the main surface of the semiconductor substrate and increases its opening ratio.

Solid state image sensing device having an overflow drain structure

Disclosed is a method of measuring physical properties of a buried channel, e.g., a generation current in a semiconductor substrate in which the buried channel is formed, a generation current of the surface of the semiconductor substrate, a channel potential and a surface potential of the buried channel. A gate ramp voltage is applied to a gate electrode formed over the buried channel and a current generated from a depletion layer at the buried channel and a gate current produced by changes in the capacitance of the buried channel are measured. The physical properties of the buried channel are obtained from the measured currents.

Method of a measuring physical properties of buried channel

Solid state image sensing device formed of charge coupled devices

A semiconductor imaging element for generating an electrical signal representing the intensity of incident light includes an avalanche photodiode, having sequential p-type, intrinsic, and n-type layers, with a compositional superlattice as the intrinsic layer, for converting incident light to an electric signal, and a switch electrically connected to the photodiode for receiving and reading out the signal. The photodiode and switch are disposed at least partially overlying each other on the same substrate. A two-dimensional array of the imaging element can be used to generate an electrical signal representing a two-dimensional picture of a material object.

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Itami, Japan

Mikihiro Kimura