Intel Corporation

Tahoe Research, Ltd.

Mihir K Roy

Mathew J Manusharow

Islam A Salama

Wei-Lun Kane Jen

Mark S Hlad

Harold Ryan Chase

Tao Wu

Brent M Roberts

William J Lambert

Debendra Mallik

Yonggang Li

Sriram Srinivasan

Stefanie M Lotz

Manohar S Konchady

Kyu Oh Lee

Yikang Deng

Yueli Liu

Yi Li

Sridhar Narasimhan

Adel A Elsherbini

Aleksandar Aleksov

Feras Eid

Robert L Sankman

Krishna Bharath

Javier Soto Gonzalez

Suddhasattwa Nad

Yidnekachew S Mekonnen

Daniel N Sobieski

Meizi Jiao

Charavana K Gurumurthy

John Stephen Guzek

Edward Allyn Burton

Kaladhar Radhakrishnan

Chong Zhang

Amanda E Schuckman

Kyu-Oh Lee

Mahadevan Suryakumar

Zheng Zhou

Stephanie M Lotz

Sriram Sriniyasan

Matthew J Manusharow

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

High density interconnect device and method

Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

High density organic bridge device and method

Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

Helical plated through-hole package inductor

A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Methods of forming a package substrate

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Method of making an inductor

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Package power delivery using plane and shaped vias

Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

Substrate conductor structure and method

Solder resist layers for coreless packages and methods of fabrication

A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.

Inductor formed in substrate

Growing community of inventors

Chandler, AZ, United States of America

Mihir K Roy