Infineon Technologies Ag

International Business Machines Corporation

Other

Infineon Technologies North America Corp.

Infineon Technologies LLC

Mihel Seitz

Venkatachalam C Jaiprakash

Rajeev Malik

Andreas Knorr

Jack Allan Mandelman

Oleg Gluschenkov

Rajarao Jammy

Jochen C Beintner

Johnathan E Faltermeier

Byeong Yeol Kim

Rama Divakaruni

Philip L Flaitz

Norbert Arnold

Carol J Heenan

Akira Sudo

Yoichi Takegawa

Ramachandra Divakaruni

Michael Patrick Chudzik

Ravikumar Ramachandran

Gregory Costrini

Werner Robl

Gerhard Kunkel

Michael Lester Wise

Stephan Wege

Thomas Goebel

Irene Lennox McStay

Woo-Tag Kang

Christian Dubuc

Irene Mcstay

The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate () made of silicon with a first hard mask layer () made of silicon oxide and an overlying second hard mask layer () made of silicon; providing a masking layer () made of silicon oxide above and laterally with respect to the second hard mask layer () made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (); providing a photoresist mask () above the masking layer () with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (); opening the masking layer () in a first plasma process using the photoresist mask (), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer () and second hard mask layer () in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate () in a fourth plasma process using the opened first hard mask layer (); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.

Method for fabricating a semiconductor structure

The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.

DRAM with very shallow trench isolation

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Pitcher-shaped active area for field effect transistor and method of forming same

A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

DRAM with vertical transistor and trench capacitor memory cells and method of fabrication

A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer. A gate electrode connected to the gate is formed using a Damascene process with insulating sidewall spacer regions being formed before the gate electrode is formed. Borderless contacts, which are self aligned, are made to the first output regions of each transistor using a Damascene process.

Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts

A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300&deg; C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300&deg; C.

Three layer aluminum deposition process for high aspect ratio CL contacts

A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

Method for fabricating a trench capacitor

A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Self-aligned contact formation using double SiN spacers

Low temperature sidewall oxidation of W/WN/poly-gatestack

Control of separation between transfer gate and storage node in vertical DRAM

A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches ( ) separating the active areas, comprising depositing a first insulating material ( ) and forming a resist ( ) over the first insulating material ( ) over at least the trenches ( ), leaving a first top portion of the first insulating material ( ) exposed. At least a second top portion of the first insulating material ( ) is removed, the resist ( ) is removed, and a second insulating material ( ) is deposited over the wafer ( ) to completely fill the isolation trenches ( ).

High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern

DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication

A method of providing isolation between element regions of a semiconductor memory device ( ). Isolation trenches ( ) are filled using several sequential anisotropic insulating material ( ) HPD-CVD deposition processes, with each deposition process being followed by an isotropic etch back to remove the insulating material ( ) from the isolation trench ( ) sidewalls. A nitride liner ( ) may be deposited after isolation trench ( ) formation. A top portion of the nitride liner ( ) may be removed prior to the deposition of the top insulating material ( ) layer.

Method for high aspect ratio gap fill using sequential HDP-CVD

Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.

Process for protecting array top oxide

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Wappingers Falls, NY, United States of America

Mihel Seitz