Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Toshiba America Electronic Components, Inc.

Mickey H Yu

Robert J Gauthier, Jr

Souvick Mitra

Alain F Loiseau

You Li

Tsung-Che Tsai

Andres Bryant

Anthony K Stamper

Brent A Anderson

Steven M Shank

Balasubramanian Pranatharthiharan

Ravikumar Ramachandran

Siva P Adusumilli

Emre Alptekin

Yves T Ngu

Edward J Nowak

Josephine B Chang

Michael A Guillorn

Lars W Liebmann

Sivananda K Kanakasabapathy

Soon-Cheon Seo

James William Adkisson

Injo Ok

Jeffrey Bowman Johnson

Brian Joseph Greene

Michael Joseph Zierak

Jerome Brett Lasky

Mujahid Muhammad

Charan V V S Surisetty

Ephrem G Gebreselasie

Shunhua Thomas Chang

Justin W Wong

Anthony C Speranza

Xiangxiang Lu

Ryoji Hasumi

Bret Philips

Tsai Tsung-Che

A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Electrostatic discharge clamp structures

A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

Structure including polycrystalline resistor with dopant-including polycrystalline region thereunder

A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.

Polysilicon resistor with continuous u-shaped polysilicon resistor elements and related method

Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

Semiconductor devices having a fin channel arranged between source and drift regions and methods of manufacturing the same

Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

Silicon-controlled rectifiers with wells laterally isolated by trench isolation regions

The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Apparatus and method to prevent integrated circuit from entering latch-up mode

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.

Electrostatic discharge devices with reduced capacitance

Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

Vertical fin-type devices and methods

Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.

High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET) technology and method for producing the same

Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.

Fin-based diode structures with a realigned feature layout

The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.

Low capacitance electrostatic discharge (ESD) devices

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

Forming stressed epitaxial layers between gates separated by different pitches

A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin.

Method for forming merged contact for semiconductor device

Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.

Growing community of inventors

Essex Jucntion, VT, United States of America

Mickey H Yu