Fujitsu Corporation

Fujitsu Semiconductor Limited

Michio Oryoji

Hisaya Sakai

Haruhito Nishibe

An insulating film is formed over a semiconductor substrate. A wiring trench formed in the insulating film reaches partway in a thickness direction of the insulating film. A via hole is disposed at an end of the wiring trench. A barrier metal film covers inner surfaces of the wiring trench and via hole. A bottom of the wiring trench and a sidewall of the via hole are connected via an inclined plane. A length of a portion of the inclined plane having an inclination angle range of 40&#xb0; to 50&#xb0; relative to a surface of the semiconductor substrate is equal to or shorter than a maximum size of a plan shape of the via hole, in a cross section which is parallel to a longitudinal direction of the wiring trench, passes a center of the via hole and perpendicular to the surface of the semiconductor surface.

Semiconductor device having wirings formed by damascene

A via hole is formed in the interlayer insulating film on a semiconductor substrate, the via hole reaching the bottom of the interlayer insulating film. A filling member fills a lower partial space in the via hole. A wiring trench continuous with the via hole as viewed in plan is formed, the wiring trench reaching partway in a thickness direction. The wiring trench is formed under the condition that an etching rate of the interlayer insulating film is faster than that of the filling member, in such a manner that a height difference between the upper surface of the filling member and the bottom of the wiring trench is half or less than half the maximum size of a plan shape of the via hole. The filling member in the via hole is removed. The inside of the via hole and wiring trench is filled with a conductive member.

Semiconductor device having wirings formed by damascene and its manufacture method

A via hole is first formed, and an embedded material is embedded in the via hole. A height of the embedded material is adjusted so that a surface thereof is between an upper surface of an SiOC film and that of an SiC film. After this, an SiN film, a TEOS film, and the SiOC film are etched by using a resist mask as a mask. However, etching of the SiOC film is stopped when a bottom of a trench formed in the SiOC film is lower than an upper surface of the embedded material and higher than that of the SiC film. Then, the resist mask and the embedded material are removed. The SiOC film is etched again by using the SiN film as a mask, and the SiN film and an exposed part of the SiC film are removed.

Method for manufacturing semiconductor device

In a via-first Dual Damascene method, after a via hole and a wiring trench are formed, an SiN film, an exposed portion of an SiC film and an exposed portion of an SiC film are removed by etching. As a result, the via hole reaches a Cu wire, and the wiring trench reaches an SiOC film. A reaction product adheres mainly to a side wall portion of the wiring trench. The reaction product also adheres to other spots, but an amount of adherence to the side wall portion is the largest. Subsequently, oxygen plasma treatment is performed for insides of the via hole and the wiring trench. As a result of this oxygen plasma treatment, the reaction product is removed.

Growing community of inventors

Kawasaki, Japan

Michio Oryoji