Sandisk Technologies Inc.

Sandisk 3D LLC

Western Digital Technologies, Inc.

Michiaki Sano

Akira Nakada

Kazuto Watanabe

Hiroshi Sasaki

Koichi Ito

Keisuke Izumi

Naohito Yanagida

Seiji Shimabukuro

Tatsuya Hinoue

Masanori Tsutsumi

Mitsuteru Mushiga

Zhen Chen

Tetsuya Yamada

Akira Takahashi

Takashi Yamaha

Katsuya Kato

Ikue Yokomizo

Ryo Hiramatsu

Hajime Yamamoto

Haruki Urata

Raghuveer S Makala

Yanli Zhang

Akio Nishida

Naoki Takeguchi

Kensuke Yamaguchi

Eiji Hayashi

Hiroaki Iuchi

Yujin Terasawa

Manabu Hayashi

Sung Tae Lee

Tae-Kyung Kim

Hiroyuki Ogawa

Liang Li

Tuan Duc Pham

Hiroyuki Kinoshita

Ken Oowada

Masatoshi Nishikawa

Zhixin Cui

Steven J Radigan

Jixin Yu

Ramy Nashed Bassely Said

Fumitaka Amano

Daxin Mao

Seje Takaki

Jongsun Sel

Akihiro Tobioka

Genta Mizuno

Yusuke Mukae

Kenji Sugiura

Junichi Ariyoshi

Yasuo Kasagi

Shuji Minagawa

Masato Miyamoto

Takashi Matsubara

Yu Ueda

Motoki Kawasaki

Kensuke Ishikawa

Keisuke Shigemura

Jo Sato

Junji Oh

Ryosuke Kaneko

Shinya Inoue

Akio Yanai

Daewung Kang

Kan Fujiwara

Hajime Kimura

Shogo Tomita

Hiroaki Namba

Yusuke Oda

Cheng Feng

Takehiro Yamazaki

Minoru Yamaguchi

Teruyuki Mine

Ryo Mochizuki

Takuya Mori

Yasunobu Azuma

Yasuke Oda

Shigenori Sato

Yiyang Gong

Tohru Toda

Yashushi Ishii

Yohei Yamada

Systems and methods for non-destructive inspection of semiconductor devices, such as three-dimensional NAND memory device, using reflective X-ray microscope computed tomographic (CT) imaging. An X-ray microscope directs a focused beam of X-ray radiation at an oblique angle onto the surface of a semiconductor wafer such that the beam passes through device structures and at least a portion of the beam is reflected by a semiconductor substrate of the wafer and detected by an X-ray detector. The wafer may be rotated about a rotation axis to obtain X-ray images of a region-of-interest (ROI) at different projection angles. A processing unit uses detected X-ray image data obtained by the X-ray detector at the different projection angles to generate a CT reconstructed image of the ROI. The CT reconstructed image may enable inspection of internal structural features, including embedded defects, in the semiconductor device in a non-destructive manner.

Systems and methods for non-destructive inspection of semiconductor devices using reflective X-ray microscope tomographic imaging

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word lines and drain select gate electrodes that contain plurality of drain-select-level electrically conductive strips which are located above the word lines, memory stack structures vertically extending through the alternating stack, drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips, and a first laterally-insulated contact via assembly including a first layer contact via structure and a first tubular insulating spacer. The first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines, and the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures.

Three-dimensional memory device containing word line contacts which extend through drain-select-level isolation structures and methods of making the same

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

Semiconductor device having edge seal and method of making thereof without metal hard mask arcing

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and an insulating spacer laterally surrounding the contact via structure and having an outer surface having a corrugated vertical cross-sectional profile in which first portions of the insulating spacer located at levels of the electrically conductive layers laterally protrude outward relative to second portions of the insulating spacer located at levels of the insulating layers.

Three-dimensional memory device including stairless word line contact structures and method of making the same

An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.

Three-dimensional memory device with punch-through-resistant word lines and methods for forming the same

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

Three-dimensional memory device with composite charge storage structures and methods for forming the same

A gas scrubber includes a canister having a rotatable spiral separator which provides a non-linear path configured to be filled with modular adsorbent material portions between a gas inlet and a gas outlet.

Spiral gas adsorption apparatus and method of using the same

An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

Three-dimensional memory device containing a replacement buried source line and methods of making the same

A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

Bonded assembly containing side bonding structures and methods of manufacturing the same

A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.

Three-dimensional memory device containing drain select isolation structures and on-pitch channels and methods of making the same without an etch stop layer

Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.

Multiple vertical TFT structures for a vertical bit line architecture

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Yokkaichi, Japan

Michiaki Sano