International Business Machines Corporation

Michele Castriotta

Stefano Sergio Oggioni

Giorgio Viero

Thomas J Brunschwiler

Gerd Schlottig

Rachel Gordin

Mauro Spreafico

Gianluca Rogiani

A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.

Integrated helical multi-layer inductor structures

A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.

Handling and positioning of metallic plated balls for socket application in ball grid array packages

A stacked via structure () adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks () belonging to three adjacent conductive layers () separated by dielectric layers (), aligned according to z axis. Connections between these conductive tracks are done with at least two vias () between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

Structure of stacked vias in multiple layer electrode device carriers

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Manfredonia, Italy

Michele Castriotta